Reliability versus yield and die location in advanced VLSI

Microelectronics Reliability

Volumn 39, Issue 6-7, 1999, Pages 741-749

  Riordan, W C ^a   Miller, R ^a   Hicks, J ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE; LOGIC DESIGN; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; RELIABILITY; SILICON WAFERS; TITANIUM COMPOUNDS; YIELD STRESS;

CMOS LOGIC PROCESS; DIE LOCATION; RELIABILITY DEFECT DENSITY; X-Y DIE POSITION; YIELD DEFECT DENSITY;

VLSI CIRCUITS;

EID: 0033147257     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(99)00095-5     Document Type: Article

References (8)

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3. J. van der Pol, F. Kuper, E Ooms, "Relation between yield and reliability of integrated circuits and application to failure rate assessment and reduction in the one digit FIT and PPM reliability era.", Proceedings of the 7th European Symposium on Reliability of Electron Devices, Failure Physics, and Analysis, 1996, pp1603-1610.
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8. W. Riordan, R. Miller, J. Sherman, J. Hicks, "Microprocessor Reliability Performance as a Function of Die Location for a 0.25u, Five Layer Metal CMOS Logic Process", IRPS, 1999, pp1-11.