Asynchronous processor survey

Computer

Volumn 30, Issue 11, 1997, Pages 67-76

  Werner, Tony ^a,b,c,d   Akella, Venkatesh ^a,e,f,g  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b HITACHI AMERICA LTD   (United States)

^c UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^d UNIVERSITY OF ARIZONA   (United States)

^e University of California Davis   (United States)

^f INDIAN INSTITUTE OF SCIENCE   (India)

^g UNIVERSITY OF UTAH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTERS; ELECTRONIC TIMING DEVICES; OPTIMIZATION; POWER CONTROL; POWER SUPPLY CIRCUITS;

ASYNCHRONOUS PROCESSOR; MODULAR DESIGN; POWER DISSIPATION;

COMPUTER SYSTEMS;

EID: 0031271356     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/2.634866     Document Type: Review

References (11)

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2. N.C. Paver, The Design and implementation of an Asynchronous Microprocessor, doctoral dissertation, Dept. of Computer Science, Univ. of Manchester, 1994.
3. A.J. Martin et al., The Design of an Asynchronous Microprocessor, Tech. Report Caltech-CS-TR-89-2, California Inst. of Technology, Pasadena, Calif., 1989.
4. J.A. Tierno et al., "A 100 MIPS GaAs Asynchronous Microprocessor," IEEE Design and Test of Computers, Summer 1994, pp. 43-49.
5. K.-R. Cho, K. Okura, and K. Asada, "Design of a 32-bit Fully Asynchronous Microprocessor (FAM)," Proc. 35th Midwest Symp. Circuits and Systems, IEEE Press, Piscataway, N.J., 1992, pp. 1,500-1,503.
6. K.-Rok Cho and K. Asada, "VLSI Oriented Design Method of Asynchronous Sequential Circuits Based on One-Hot State Code and Two-Transistor AND Logic," Proc. Int'l Symp. Computers and Systems, IEEE Press, Piscataway, N.J., 1991, pp. 1,793-1,796.
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8. R.F. Sproull, I.E. Sutherland, and C.A. Molnar, Counterflow Pipeline Processor Architecture, Tech. Report SMLI TR-94-25, Sun Microsystems Laboratories, Mountain View, Calif., Apr. 1994.
9. M.E. Dean, STRIP: A Self-Timed RISC Processor, Tech. Report CSL-TR-92-543, Stanford Univ., Stanford, Calif., July 1992.
10. T. Nanya et al., "TITAC: Design of a Quasi-Delay-Insensitive Microprocessor," IEEE Design and Test of Computers, Summer 1994, pp. 50-53.
11. W.F. Richardson and E. Brunvand, "Fred: An Architecture for a Self-Timed Decoupled Computer," Proc. Second Int'l Symp. Advanced Research in Asynchronous Circuits and Systems, IEEE Press, Piscataway, N.J., 1996, pp. 60-68.