Area-Efficient Architectures for the Viterbi Algorithm—Part I: Theory

IEEE Transactions on Communications

Volumn 41, Issue 4, 1993, Pages 636-644

  Shung, C Bernard ^a   Lin, Horng Dar ^b   Cypher, Robert ^c   Siegel, Paul H ^c   Thapar, Hemant K ^d  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b LUCENT TECHNOLOGIES   (United States)

^c IBM ALMADEN RESEARCH CENTER   (United States)

^d IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL DESIGN; COMMUNICATION SYSTEMS; DECODING; PIPELINE PROCESSING SYSTEMS; SIGNAL PROCESSING;

ADD COMPARE SELECT (ACS); AREA EFFICIENT ARCHITECTURE; INTERCONNECTION WIRES; INTERNAL PARALLELISM; VITERBI ALGORITHM;

ALGORITHMS;

EID: 0027585274     PISSN: 00906778     EISSN: None     Source Type: Journal    
DOI: 10.1109/26.223789     Document Type: Article

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