메뉴 건너뛰기




Volumn 6, Issue , 1999, Pages

Equivalence classes of circuit mutants for experimental design

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT MUTANTS;

EID: 0032671582     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article
Times cited : (7)

References (12)
  • 1
    • 0032624124 scopus 로고    scopus 로고
    • Design of experiments in CAD: Context and new data sets for ISCAS'QQ
    • May
    • F. Brglez and R. Drechsler. Design of Experiments in CAD: Context and New Data Sets for ISCAS'QQ. In IEEE 1999 International Symposium Circuit and Systems - ISCAS'99, May 1999. A reprint also accessible from http:/www.cbl.ncru.~du/publications/Xi999-ISCAS-Brgl~=.
    • (1999) IEEE 1999 International Symposium Circuit and Systems - ISCAS'99
    • Brglez, F.1    Drechsler, R.2
  • 2
    • 0009973892 scopus 로고    scopus 로고
    • Synthesis of wiring signa1,ure-invariant equivalence class circuit mutants and applications to benchmarking
    • Feb
    • Debabrata Ghosh, Nevin Kapur, Justin E. Harlow 111, and Franc Brglee. Synthesis of Wiring Signa1,ure-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking. In Proceedings, Design Automation and Test m Eumpe, pages 656-663, Feb 1998. A.lso available at http: //www.chl .ncsu.du/publications/#l998-DATE-Oho.h.
    • (1998) Proceedings, Design Automation and Test M Eumpe , pp. 656-663
    • Ghosh, D.1    Kapur, N.2    Harlow III, J.E.3    Brglee, F.4
  • 4
    • 0030695767 scopus 로고    scopus 로고
    • Generation of synthetic sequential benchmark circuits
    • February
    • Michael Hutton, J.P. Grossman, J. Rose and D. Corneil. Generation of Synthetic Sequential Benchmark Circuits. In AGM Symposium on FPGAs, pages 149-155, February 1997. Available from http://www.aacg.toront.edu/-jayar/ puh~fpuha.ht~l.
    • (1997) AGM Symposium on FPGAs , pp. 149-155
    • Hutton, M.1    Grossman, J.P.2    Rose, J.3    Corneil, D.4
  • 5
    • 84883745291 scopus 로고    scopus 로고
    • Characterization and parameterized random generation of combinational benchmark circuits
    • To appear
    • Michael Hutton, J.P. Grossman, J. Rose and D. Corneil. Characterization and Parameterized Random Generation of Combinational Benchmark Circuits. IEEE Trans. Computer-Aided Design, 1999. To appear. Postscript available from http://www.ecg.toronto.sdu/-jayarlpubsfpubs. htm1
    • (1999) IEEE Trans. Computer-Aided Design
    • Hutton, M.1    Grossman, J.P.2    Rose, J.3    Corneil, D.4
  • 6
    • 0029702218 scopus 로고    scopus 로고
    • A method for generating random circuits and its application to routability measurement
    • February
    • J. Darnauer and W. Dai. A Method for Generating Random Circuits and its Application to Routability Measurement. In 4th ACM/SIGDA Int'l Symp. on FPGAs, FPGA96, pages 66-72, February 1996.
    • (1996) 4th ACM/SIGDA Int'l Symp. on FPGAs, FPGA96 , pp. 66-72
    • Darnauer, J.1    Dai, W.2
  • 7
    • 84883795327 scopus 로고    scopus 로고
    • Equivalence classes of sequential circuit mutants for experimental design
    • CS Dept., NCSU, Box 7550, Raleigh, NC 27695, March
    • D. Ghosh and F. Brglez. Equivalence Classes of Sequential Circuit Mutants for Experimental Design. Technical Report 1999-TROCBL-02-Ghosh, CBL, CS Dept., NCSU, Box 7550, Raleigh, NC 27695, March 1999. Also available at http: //www.cbl.ncsu.sdu/publicationa/-#1999-TROCBL-OZ-Chosh
    • (1999) Technical Report 1999-TROCBL-02-Ghosh, CBL
    • Ghosh, D.1    Brglez, F.2
  • 9
    • 0029547599 scopus 로고
    • PROP: A recursive paradigm for area- efficient and performance oriented partitioning of large fpisa netlists
    • November
    • R. Kuinar and F. Brglez. PROP: .A Recursive Paradigm for Area- Efficient and Performance Oriented Partitioning of Large FPISA Netlists. In IEEE International Conference on Computer-Aided Design. pages 644-649,November 1995.
    • (1995) IEEE International Conference on Computer-Aided Design. , pp. 644-649
    • Kuinar, R.1    Brglez, F.2
  • 10
    • 84883798830 scopus 로고
    • MCNC, Research Triangle Park, N.C. (Over 600 pages, distributed to over 60 teaching and research universities worldwide)
    • K. Kozminski, (Ed.). OASISZ.0 User's Guide. MCNC, Research Triangle Park, N.C. 27709, 1992. (Over 600 pages, distributed to over 60 teaching and research universities worldwide).
    • (1992) OASISZ.O User's Guide , pp. 27709
    • Kozminski, K.1
  • 11
    • 84957870821 scopus 로고    scopus 로고
    • VPR: A New packing, placement and routing tool for fpga research
    • August
    • V. Beta and J. Rose. VPR: A New Packing, Placement and Routing Tool for FPGA Research. In Proceedings of the 7th International Workshop on Fteld-Programmable Logtc, pages 213-222, August 1997. Software and postscript of paper can be downloaded from http://www.aecg.toronto.edu/-=ughn/vp=/vp=.html.
    • (1997) Proceedings of the 7th International Workshop on Fteld-Programmable Logtc , pp. 213-222
    • Beta, V.1    Rose, J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.