Analysis and evaluation of address arithmetic capabilities in custom DSP architectures

Design Automation for Embedded Systems

Volumn 4, Issue 1, 1999, Pages 5-22

  Sudarsanam, Ashok ^a   Liao, Stan ^b   Devadas, Srinivas ^c  

^a Princeton University   (United States)

^b SYNOPSYS INC   (United States)

^c MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); COMPUTER ARCHITECTURE; COMPUTER SYSTEMS PROGRAMMING; DIGITAL ARITHMETIC; PROGRAM COMPILERS; RESPONSE TIME (COMPUTER SYSTEMS); ROM; STORAGE ALLOCATION (COMPUTER);

AUTO-INCREMENT/DECREMENT ARITHMETIC;

DIGITAL SIGNAL PROCESSING;

EID: 0032665834     PISSN: 09295585     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008869915325     Document Type: Article

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