Instruction set design and optimizations for address computation in DSP architectures

Proceedings of the International Symposium on System Synthesis

Volumn , Issue , 1996, Pages 102-107

  Araujo, Guido ^a   Sudarsanam, Ashok ^a   Malik, Sharad ^a  

^a PRINCETON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; DIGITAL ARITHMETIC; GRAPH THEORY; OPTIMIZATION; PROGRAM PROCESSORS; SHIFT REGISTERS; STANDARDS;

ADDRESS GENERATION UNIT; ALLOCATING ADDRESS REGISTERS; GRAPH COLORING TECHNIQUE; INSTRUCTION SET ARCHITECTURE; INSTRUCTION SET DESIGN; SOURCE PROGRAM;

DIGITAL SIGNAL PROCESSING;

EID: 0030399297     PISSN: 10801820     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)