5Gbit/s 2:1 multiplexer fabricated in 0.35μm CMOS and 3Gbit/s 1:2 demultiplexer fabricated in 0.5 μm CMOS technology

Electronics Letters

Volumn 35, Issue 19, 1999, Pages 1631-1633

  Runge, K ^a   Thomas, P B ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; EMITTER COUPLED LOGIC CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE;

DEMULTIPLEXERS;

MULTIPLEXING EQUIPMENT;

EID: 0032660898     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19991105     Document Type: Article

References (4)

1. WONG. H.-S.P., FRANK, D.J., SOLOMON, P., WANN, C.H.J., and WELSER, J.J.: 'Nanoscale CMOS', Proc. IEEE. Special Issue Quantum Devices Applications, April 1999,
2. TANABE, A., SODA, M., NAKAHARA, Y., TAMURA, T., YOSHIDA, K., and FURUKAWA, A.: 'A single-chip 2.4Gb/s CMOS optical receiver IC with low substrate cross-talk preamplifier', IEEE J. Solid-State Circuits, December 1998, 33, (12)
3. NAKAMURA, K., FUCKAISHI, M., ABIKO, H., MATSUMOTO, A., and YOTSUYANAGI, M.: 'A 6Gb/s CMOS phase detecting DEMUX module using half-frequency clock'. 1998 Symp. VLSI Circuits Dig. Tech. Papers, 1998, pp. 196-198
4. KURISU, M., KANEKO, M., SUZAKI, T., TANABE, A., TOGO, M., FURAKAWA, A., TAMURA, T., NAKAJIMA, K., and YOSHIDA, K.: '2.8Gb/s 176mW byte-interleaved and 3.0Gb/s 118mW bitinterleaved 8:1 multiplexers'. ISSCC Dig. Tech. Papers, 1996, pp. 122-123