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Volumn 9, Issue 2 PART 3, 1999, Pages 3553-3556

New logic circuits based on SFQ signals

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; GATES (TRANSISTOR); JOSEPHSON JUNCTION DEVICES; MAGNETIC FLUX; MAGNETIC STORAGE; NUMERICAL METHODS; SIGNAL PROCESSING;

EID: 0032660169     PISSN: 10518223     EISSN: None     Source Type: Journal    
DOI: 10.1109/77.783797     Document Type: Article
Times cited : (8)

References (7)
  • 1
    • 0026116572 scopus 로고    scopus 로고
    • "RSFQ logic /memory family: A new Josephson-junction technology for sub-terahertz-clockfrequency digital systems", IEEE Trans. Appl. Superconduct., vol. 1, pp. 3-28, Mar. 1991
    • K. K. Likharev and V. K. Semenov, "RSFQ logic /memory family: A new Josephson-junction technology for sub-terahertz-clockfrequency digital systems", IEEE Trans. Appl. Superconduct., vol. 1, pp. 3-28, Mar. 1991
    • Likharev, K.K.1    Semenov, V.K.2
  • 2
    • 0029373594 scopus 로고    scopus 로고
    • "Magnetic imaging of moat-guarded superconducting electronic circuits", Appl. Phys. Lett., vol. 67(12), pp. 1769-1771,1995
    • M. Jeffery, T. V. Duzer, J. R. Kirtley and M. B. Ketchen, "Magnetic imaging of moat-guarded superconducting electronic circuits", Appl. Phys. Lett., vol. 67(12), pp. 1769-1771,1995
    • Jeffery, M.1    Duzer, T.V.2    Kirtley, J.R.3    Ketchen, M.B.4
  • 3
    • 33747715367 scopus 로고    scopus 로고
    • "Evaluation of trapped magnetic flux for Josephson 4-kbit RAMs", Extended Abstracts of 1995 Int. Superconductive Electronics Conf., (Nagoya, 1995), pp. 192-194.
    • S. Nagasawa, H. Numata, C. Kato and S. Tahara, "Evaluation of trapped magnetic flux for Josephson 4-kbit RAMs", Extended Abstracts of 1995 Int. Superconductive Electronics Conf., (Nagoya, 1995), pp. 192-194.
    • Nagasawa, S.1    Numata, H.2    Kato, C.3    Tahara, S.4
  • 4
    • 33747724248 scopus 로고    scopus 로고
    • "A model of the logic circuit based on partiel izecl information bits and logic specification with temporal logic", Trans. IECE D. vol. 68(2), pp. 195-196, Feb, 1985
    • Y. Takai, T. Nakamura and Y. Shigei, "A model of the logic circuit based on partiel izecl information bits and logic specification with temporal logic", Trans. IECE D. vol. 68(2), pp. 195-196, Feb, 1985, (in Japanese)
    • (In Japanese)
    • Takai, Y.1    Nakamura, T.2    Shigei, Y.3
  • 5
    • 33747709624 scopus 로고    scopus 로고
    • "A Josephson intergated circuit simulator (JSIM) for superconductive electronics application", Extended Abstracts of 1989 Int. Superconductive Electronics Conf., (Tokyo. 1989) pp. 407-410.
    • E. S. Fang and T. V. Duzer, "A Josephson intergated circuit simulator (JSIM) for superconductive electronics application", Extended Abstracts of 1989 Int. Superconductive Electronics Conf., (Tokyo. 1989) pp. 407-410.
    • Fang, E.S.1    Duzer, T.V.2
  • 6
    • 33747679545 scopus 로고    scopus 로고
    • "Fabrication process for submicron Josephson junctions", 1993 Int. Superconductive Electronics Conf. (Boulder, 1993) pp.280-281.
    • H. Numata, S. Nagasawa and S. Tahara, "Fabrication process for submicron Josephson junctions", Extended Abstracts of 1993 Int. Superconductive Electronics Conf. (Boulder, 1993) pp.280-281.
    • Extended Abstracts of
    • Numata, H.1    Nagasawa, S.2    Tahara, S.3
  • 7
    • 0029325870 scopus 로고    scopus 로고
    • "A 380ps, 9.5mW Josephson 4-Kbit RAM operated at a high bit yield", IEEE Trans. Appl. Superconduct., vol. 5, pp. 2447-2452, Jun. 1995.
    • S. Nagasawa, Y. Hashimoto, H. Numata and S. Tahara, "A 380ps, 9.5mW Josephson 4-Kbit RAM operated at a high bit yield", IEEE Trans. Appl. Superconduct., vol. 5, pp. 2447-2452, Jun. 1995.
    • Nagasawa, S.1    Hashimoto, Y.2    Numata, H.3    Tahara, S.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.