A gigabyte-per-second parollei fiber optic network interface for multimedia applications

IEEE Network

Volumn 13, Issue 1, 1999, Pages 20-28

  Raghavan, B ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; BROADBAND NETWORKS; CMOS INTEGRATED CIRCUITS; INTERFACES (COMPUTER); MICROPROCESSOR CHIPS; MULTIMEDIA SYSTEMS; PARALLEL PROCESSING SYSTEMS;

GIGABYTE-PER-SECOND PARALLEL FIBER OPTIC NETWORK INTERFACES; MEDIUM ACCESS CONTROL (MAC);

FIBER OPTIC NETWORKS;

EID: 0032651496     PISSN: 08908044     EISSN: None     Source Type: Journal    
DOI: 10.1109/65.750446     Document Type: Article

References (6)

1. J. Silberman et al., "A 1.0GHz single-issue 64b PowerPC integer processor, 1998 lEEEInfl. Solid-State Circuits Conf., Feb. 1998, pp. 230-31.
2. B. Sano, B. Madhavan, and A. F. J. Levi, '8 Gb/s CMOS interface for parallel fiber optic links,' Elect. Lett., vol. 32, no. 24, Nov. 1996, pp. 2262-63.
3. B. Sano and A. F. J. Levi, "Networks for the professional campus environment," Multimedia Technology for Applications, Piscataway, NJ: IEEE Press, 1998, pp. 413-27.
4. R. C. Walker et al., "A 10 Gb/s Si-Bipolar TX/RX Chipset for Computer Data Transmission," Proc. 1998 IEEE Infl. Solid-Slate Circuits Conf., Feb. 1998, pp. 302-3.
5. A. P. Kanjamala and A. F. J. Levi, "Subpicosecond skew in multimode fibre ribbon for synchronous data transmission," Elect.. Lett., vol. 31, no. 16, 1995, pp. 1376-77.
6. ANSI X3.148-1988, "Fiber Distributed Data Interface (FDDI) -Token Ring Physical Layer," Nov. 1988.