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Volumn 32, Issue 24, 1996, Pages 2262-2263

8Gbit/s CMOS interface for parallel fibre-optic interconnects

Author keywords

CMOS integrated circuits; Fibre optics; Optical interconnections; Vertical cavity surfaces emitting lasers

Indexed keywords

BUFFER CIRCUITS; CMOS INTEGRATED CIRCUITS; COMMUNICATION CHANNELS (INFORMATION THEORY); FIBER OPTIC NETWORKS; INTERFACES (COMPUTER); OPTICAL LINKS;

EID: 0030287617     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19961502     Document Type: Article
Times cited : (5)

References (4)
  • 4
    • 0029696337 scopus 로고    scopus 로고
    • A novel high speed low skew clock distribution scheme in 0.8μm CMOS
    • Atlanta, Georgia, 12-15 May IEEE cat #96CH35876, ISBN 0-7803-3073-0
    • MADHAVAN. B., SANO. B., and LEVI, A.F.J.: 'A novel high speed low skew clock distribution scheme in 0.8μm CMOS". IEEE Int. Symp. Circuits and Syst., Atlanta, Georgia, 12-15 May 1996, Vol. 4, pp. 149-152 (IEEE cat #96CH35876, ISBN 0-7803-3073-0)
    • (1996) IEEE Int. Symp. Circuits and Syst. , vol.4 , pp. 149-152
    • Madhavan, B.1    Sano, B.2    Levi, A.F.J.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.