Single Electron Transfer Logic Gate Family

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 38, Issue 1 B, 1999, Pages 433-438

  Yoshikawa, Nobuyuki ^a   Fukuzato, Chikashi ^a   Sugahara, Masanori ^a  

^a YOKOHAMA NATIONAL UNIVERSITY   (Japan)

Author keywords

1D array; Coulomb blockade; Logic circuit; Monte carlo simulation; SET transistor; Single electron tunneling; Tunnel junction

Indexed keywords

COMPUTER SIMULATION; ELECTRIC NETWORK ANALYSIS; ELECTRON TUNNELING; LOGIC CIRCUITS; MONTE CARLO METHODS; TIMING CIRCUITS; TRANSISTORS; TUNNEL JUNCTIONS;

SINGLE ELECTRON TUNNELING (SET) TRANSISTORS;

LOGIC GATES;

EID: 0032606926     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/JJAP.38.433     Document Type: Article

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