Complementary digital logic using resistively coupled single-electron transistor

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 35, Issue 2 SUPPL. B, 1996, Pages 1140-1145

  Yoshikawa, Nobuyuki ^a   Jinguu, Yasuyuki ^a   Ishibashi, Hiroshi ^a   Sugahara, Masanori ^a  

^a YOKOHAMA NATIONAL UNIVERSITY   (Japan)

Author keywords

C SET; Complementary logic; Coulomb blockade; Flip flop; R SET; SET transistor; Shot noise; Single electron logic; Single electron tunneling effect

Indexed keywords

CALCULATIONS; CAPACITANCE; DIGITAL CIRCUITS; ELECTRIC RESISTANCE; ELECTRON TUNNELING; FLIP FLOP CIRCUITS; LOGIC CIRCUITS; MONTE CARLO METHODS; SEMICONDUCTOR JUNCTIONS; SHOT NOISE;

COMPLEMENTARY DIGITAL LOGIC; COULOMB BLOCKADE; SINGLE ELECTRON LOGIC; SINGLE ELECTRON TRANSISTOR; SINGLE ELECTRON TUNNELING EFFECT; TUNNEL JUNCTION;

TRANSISTORS;

EID: 0030078909     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/jjap.35.1140     Document Type: Article

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