How good are slicing floorplans?

Integration, the VLSI Journal

Volumn 23, Issue 1, 1997, Pages 61-73

  Young, F Y ^a   Wong, D F ^a  

^a University of Texas at Austin   (United States)

Author keywords

Circuit placement; Floorplan design; Rectangle packing; Slicing floorplan

Indexed keywords

ELECTRONICS PACKAGING; MATHEMATICAL MODELS; NUMERICAL ANALYSIS; RECURSIVE FUNCTIONS; THEOREM PROVING; VLSI CIRCUITS;

FLOORPLAN DESIGN; SHAPE FLEXIBILITY; SLICING FLOORPLAN;

INTEGRATED CIRCUIT LAYOUT;

EID: 0031250640     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9260(97)00014-X     Document Type: Article

References (6)

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3. D.P. Lapotin, S.W. Director, A new algorithm for floorplan design, Proc. IEEE Internat. Conf. on Computer-Aided Design, 1985, pp. 143-145.
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5. T. Tamanouchi, K. Tamakashi, T. Kambe, Hybrid floorplanning based on partial clustering and module restructuring, Proc. IEEE Internat. Conf. on Computer-Aided Design, 1996, pp. 478-483.
6. D.F. Wong, C.L. Liu, A new algorithm for floorplan design, Proc. 23rd ACM/IEEE Design Automation Conf., 1986, pp. 101-107.