Characterization of snap back breakdown and its temperature dependence up to 300°C including circuit level model and simulation

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 3510, Issue , 1998, Pages 64-73

  Uffmann, Dirk ^a  

^a LEIBNIZ UNIVERSITY HANNOVER   (Germany)

Author keywords

Avalanche induced parasitic bipolar breakdown; Electrical overstress; Electrostatic discharge; EOS; ESD; MOS; Parameter extraction; Snap back breakdown; Sustaining voltage; Temperature dependence

Indexed keywords

COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC BREAKDOWN; ELECTRIC CURRENT MEASUREMENT; ELECTROSTATICS; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; MOSFET DEVICES; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR JUNCTIONS; THERMAL EFFECTS; VOLTAGE MEASUREMENT;

AVALANCHE INDUCED PARASITIC BIPOLAR BREAKDOWN; ELECTRICAL OVERSTRESS; ELECTROSTATIC DISCHARGE; PARAMETER EXTRACTION; SNAP BACK BREAKDOWN; SUSTAINING VOLTAGE; TEMPERATURE DEPENDENCE;

CMOS INTEGRATED CIRCUITS;

EID: 0032404665     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.324393     Document Type: Conference Paper

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