Simulation & modeling: Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high-current simulations

IEEE Circuits and Devices Magazine

Volumn 13, Issue 2, 1997, Pages 7-10

  Amerasekera, Ajith ^a   Chang, Mi Chang ^a   Duvvury, Charvaka ^a   Ramaswamy, Sridhar ^b  

^a TEXAS INSTRUMENTS   (United States)

^b UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION THEORY; BIPOLAR TRANSISTORS; COMPUTER AIDED DESIGN; COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; COMPUTER SOFTWARE; ELECTRIC DISCHARGES; MATHEMATICAL MODELS; OPTIMIZATION; PARAMETER ESTIMATION;

CIRCUIT LEVEL ELECTROSTATIC DISCHARGE; METAL OXIDE SEMICONDUCTOR (MOS) SNAPBACK; PARAMETER EXTRACTION METHODOLOGY; PARASITIC BIPOLAR ACTION; SOFTWARE PACKAGE MEDICI; SOFTWARE PACKAGE SPICE;

MOS DEVICES;

EID: 0031097505     PISSN: 87553996     EISSN: None     Source Type: Journal    
DOI: 10.1109/101.583606     Document Type: Article

References (9)

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2. th IRPS, P.141-150, 1992.
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8. R.W. Dutton. "Bipolar Transistor Modeling of Avalanche Generation for Computer Circuit Simulation", IEEE Trans. Elec. Dev., ED-22, p.334-338, 1975.
9. M. Pinto-Guedes, P. Chan, "A Circuit Simulation Model For Bipolar-Induced Breakdown in MOSFET," IEEE Trans. Comp. Aid. Des., CAD-7, p.289-294, 1988.