Instruction scheduling to reduce switching activity of off-chip buses for low-power systems with caches

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E81-A, Issue 12, 1998, Pages 2621-2629

  Tomiyama, Hiroyuki ^a   Ishihara, Tohru ^a   Inoue, Akihiko ^a   Yasuura, Hiroto ^a  

^a KYUSHU UNIVERSITY   (Japan)

Author keywords

Caches; Compiler optimization; Instruction scheduling; Low power

Indexed keywords

ALGORITHMS; BUFFER STORAGE; MICROPROCESSOR CHIPS; MINIMIZATION OF SWITCHING NETS; PROGRAM COMPILERS;

INSTRUCTION SCHEDULING; OFF-CHIP BUSES;

EMBEDDED SYSTEMS;

EID: 0032320587     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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