Single-electron memories

VLSI Design

Volumn 8, Issue 1-4, 1998, Pages 219-223

  Wasshuber, Christoph ^a,b,c   Kosina, Hans ^a,b,d,e   Selberherr, Siegfried ^a,b,d,f,g,h  

^a INSTITUTE FOR MICROELECTRONICS   (Austria)

^b VIENNA UNIVERSITY OF TECHNOLOGY   (Austria)

^c UNIVERSITY OF TOKYO   (Japan)

^d Vienna University of Technology ^*

^e Inst für Flexible Automation

^f Inst F Allg Elektrotech E   (Austria)

^g Institut für Mikroelektronik

^h ASSOCIATION FOR COMPUTING MACHINERY   (United States)

Author keywords

Memory; Random background charge; Simulation; Single electron tunneling

Indexed keywords

COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; ELECTRON TUNNELING; LITHOGRAPHY;

SINGLE-ELECTRON MEMORY CHIPS;

MICROPROCESSOR CHIPS;

EID: 0032314822     PISSN: 1065514X     EISSN: None     Source Type: Journal    
DOI: 10.1155/1998/83017     Document Type: Article

References (12)

1. Fulton, T. A. and Dolan, G. J., Observation of single-electron charging effects in small tunnel junctions. Physical Review Letters, 59(1), 109-112, July 1987.
2. Averin, D. V. and Likharev, K. K. (1992). Possible applications of the single charge tunneling. In H. Grabert and M. H. Devoret, editors, Single Charge Tunneling - Coulomb Blockade Phenomena in Nanostructures, Chapter 9, 311-332. Plenum Press and NATO Scientific Affairs Division, New York and London.
3. Chen, W., Ahmed, H. and Nakazato, K., Coulomb blockade at 77 K in nano-scale metallic islands in a lateral nano-structure. Applied Physics Letters, 66(24), 3383-3384, June 1995.
4. Yano, K., Ishii, T., Hashimoto, T., Kobayashi, T., Murai, F. and Seki, K. (1994). Room-temperature single-electron devices. In Extended Abstracts of the International Conference on Solid State Devices and Materials, pp. 325-327, Yokohama.
5. Wasshuber, C. and Kosina, H. (1997). A single-electron device and circuit simulator. Superlattices and Microstructures, 21(1), 37-42.
6. Web-page of SIMON. http://members.magnet.at/catsmeow/ and http://www.iue.tuwien.ac.at/software/simon.html.
7. Korotkov, A. N., Chen, R. H. and Likharev, K. K., Possible performance of capacitively coupled single-electron transistors in digital circuits. Journal of Applied Physics, 78(4), 2520-2530, August 1995.
8. Nakazato, K. and Ahmed, H., The multiple-tunnel junction and its application to single-electron memory and logic circuits. Japanese Journal of Applied Physics, 34(Part1, 2B), pp. 700-706, February 1995.
9. Lent, C. S., Tougaw, P. D. and Porod, W. A. Bistable quantum cell for cellular automata. In Int. Workshop on Computational Electronics, pp. 163-166, May 1992.
10. 0-independent single-electron systems. In Int. Workshop on Computational Electronics, p. 42.
11. Nakazato, K. Blaikie, R. J. and Ahmed, H., Single-electron memory. Journal of Applied Physics, 75(10), 5123-5134, May 1994.
12. Yano, K., Ishii, T., Sano, T., Mine, T., Murai, F. and Seki, K. (1996). Single-electron-memory integrated circuit for giga-to-tera bit storage. IEEE International Solid-State Circuits Conference, pp. 266-267.