메뉴 건너뛰기




Volumn 26, Issue 1-2, 1998, Pages 41-54

Sequential test generators: Past, present and future

Author keywords

Automatic test pattern generation; Sequential circuit test generation; Structure based testing; Test generation algorithms

Indexed keywords

ALGORITHMS; AUTOMATA THEORY; ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUIT TESTING; SEQUENTIAL CIRCUITS;

EID: 0032307319     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/s0167-9260(98)00020-0     Document Type: Article
Times cited : (9)

References (33)
  • 1
    • 0027556721 scopus 로고
    • A tutorial on built-in self-test part 1: Principles
    • V.D. Agrawal, C.R. Kime, K.K. Saluja, A tutorial on built-in self-test part 1: principles, IEEE Des. Test Comput. 10 (2) (1993) 73-82.
    • (1993) IEEE Des. Test Comput. , vol.10 , Issue.2 , pp. 73-82
    • Agrawal, V.D.1    Kime, C.R.2    Saluja, K.K.3
  • 2
    • 0027610022 scopus 로고
    • A tutorial on built-in self-test part 2: Applications
    • V.D. Agrawal, C.R. Kime, K.K. Saluja, A tutorial on built-in self-test part 2: applications, IEEE Des. Test Comput. 10 (3) (1993) 69-77.
    • (1993) IEEE Des. Test Comput. , vol.10 , Issue.3 , pp. 69-77
    • Agrawal, V.D.1    Kime, C.R.2    Saluja, K.K.3
  • 3
    • 0016485480 scopus 로고
    • Polynomially complete fault detection problems
    • P.H. Ibarra, S.K. Sahni, Polynomially complete fault detection problems, IEEE Trans. Comput. 24 (3) (1975) 242-249.
    • (1975) IEEE Trans. Comput. , vol.24 , Issue.3 , pp. 242-249
    • Ibarra, P.H.1    Sahni, S.K.2
  • 4
    • 0027698840 scopus 로고
    • An effiecient algorithms for sequential circuit test generation
    • T.P. Kelsey, K.K. Saluja, S.Y. Lee, An effiecient algorithms for sequential circuit test generation, IEEE Trans. Comput. 42 (11) (1993) 1361-1371.
    • (1993) IEEE Trans. Comput. , vol.42 , Issue.11 , pp. 1361-1371
    • Kelsey, T.P.1    Saluja, K.K.2    Lee, S.Y.3
  • 5
    • 84911547644 scopus 로고
    • Programmed algorithms to compute tests and to detect and distinguish between failures in logic circuit
    • J. Roth, W.G. Bouricius, P.R. Schneider, Programmed algorithms to compute tests and to detect and distinguish between failures in logic circuit, IEEE Trans. Electron. Comput. 16 (10) (1967) 567-580.
    • (1967) IEEE Trans. Electron. Comput. , vol.16 , Issue.10 , pp. 567-580
    • Roth, J.1    Bouricius, W.G.2    Schneider, P.R.3
  • 6
    • 0016961573 scopus 로고
    • A nine-valued circuit model for test generation
    • P. Muth, A nine-valued circuit model for test generation, IEEE Trans. Comput. 25 (6) (1976) 630-636.
    • (1976) IEEE Trans. Comput. , vol.25 , Issue.6 , pp. 630-636
    • Muth, P.1
  • 7
    • 0019543877 scopus 로고
    • An implicit enumeration algorithms to generate test for combinational circuits
    • P. Goel, An implicit enumeration algorithms to generate test for combinational circuits, IEEE Trans. Comput. 30 (3) (1981) 215-222.
    • (1981) IEEE Trans. Comput. , vol.30 , Issue.3 , pp. 215-222
    • Goel, P.1
  • 8
    • 0020923381 scopus 로고
    • On the acceleration of test generation algortihms
    • H. Fujiwara, T. Shimono, On the acceleration of test generation algortihms, IEEE Trans. Comput. 32 (12) (1983) 1137-1144.
    • (1983) IEEE Trans. Comput. , vol.32 , Issue.12 , pp. 1137-1144
    • Fujiwara, H.1    Shimono, T.2
  • 9
    • 0017788576 scopus 로고
    • EBT: A comprehensive test generation technique for highly sequential circuits
    • June
    • R. Marlett, EBT: a comprehensive test generation technique for highly sequential circuits, Proc. Design automation Conf., June 1978. pp. 332-339.
    • (1978) Proc. Design Automation Conf. , pp. 332-339
    • Marlett, R.1
  • 10
    • 0024138663 scopus 로고
    • The BACK algorithm for sequential test generation
    • August
    • W.T. Cheng, The BACK algorithm for sequential test generation, Proc. Int. Conf. on Comupter Design, August 1988, pp. 66-69.
    • (1988) Proc. Int. Conf. on Comupter Design , pp. 66-69
    • Cheng, W.T.1
  • 11
    • 0024142846 scopus 로고
    • SPLIT circuit model for test generation
    • W.T. Cheng, SPLIT circuit model for test generation, Proc. Design automation Conf., 1988, pp. 96-101
    • (1988) Proc. Design Automation Conf. , pp. 96-101
    • Cheng, W.T.1
  • 12
    • 0027072656 scopus 로고
    • HITEC: A test generation package for sequential circuits
    • February
    • T. Niermann, J.H. Patel, HITEC: a test generation package for sequential circuits, Proc. European Test Conf., February 1991, pp. 214-218.
    • (1991) Proc. European Test Conf. , pp. 214-218
    • Niermann, T.1    Patel, J.H.2
  • 13
    • 0025565157 scopus 로고
    • Proofs: A fast memory efficient sequential circit fault simulator
    • June
    • T. Niermann, W.T. Cheng, J.H. Patel, Proofs: a fast memory efficient sequential circit fault simulator, Proc. Design Automat. Conf., June 1990, pp. 535-540.
    • (1990) Proc. Design Automat. Conf. , pp. 535-540
    • Niermann, T.1    Cheng, W.T.2    Patel, J.H.3
  • 14
    • 0024646172 scopus 로고
    • GENTEST: An automatic test generation system for sequential circuits
    • W.T. Cheng, T. Chakraborty, GENTEST: an automatic test generation system for sequential circuits, IEEE Comput. 22 (4) (1989) 43-49.
    • (1989) IEEE Comput. , vol.22 , Issue.4 , pp. 43-49
    • Cheng, W.T.1    Chakraborty, T.2
  • 15
    • 0026168663 scopus 로고
    • A test-pattern-generation algorithm for sequential circuits
    • E. Auth, M.H. Schulz, A test-pattern-generation algorithm for sequential circuits, IEEE Des. Test Comput. 8 (2) (1991) 72-86.
    • (1991) IEEE Des. Test Comput. , vol.8 , Issue.2 , pp. 72-86
    • Auth, E.1    Schulz, M.H.2
  • 16
    • 0024891271 scopus 로고
    • ESSENTIAL: An efficient self-learning test pattern generation algorithm for sequential circuits
    • M.H. Schulz, E. Auth, ESSENTIAL: an efficient self-learning test pattern generation algorithm for sequential circuits, Proc. ITC (1989) 28-37.
    • (1989) Proc. ITC , pp. 28-37
    • Schulz, M.H.1    Auth, E.2
  • 17
    • 0023558527 scopus 로고
    • SOCRATES: A highly efficient automatic test pattern generation system
    • September
    • M.H. Schulz, E. Trischler, T.M. Sarfert, SOCRATES: a highly efficient automatic test pattern generation system, Proc. Int. Test Conf., September 1987, pp. 1016-1026.
    • (1987) Proc. Int. Test Conf. , pp. 1016-1026
    • Schulz, M.H.1    Trischler, E.2    Sarfert, T.M.3
  • 18
    • 0018524018 scopus 로고
    • Controllability/observability analysis for digital circuits
    • L.H. Goldstein, Controllability/observability analysis for digital circuits, IEEE Trans. Circuits Systems, Vol. CAS-26 (9) (1979) 685-693.
    • (1979) IEEE Trans. Circuits Systems , vol.CAS-26 , Issue.9 , pp. 685-693
    • Goldstein, L.H.1
  • 20
    • 0026153304 scopus 로고
    • Test generation and verification for highly sequential circuits
    • A. Ghosh, S. Devadas, A.R. Newton, Test generation and verification for highly sequential circuits, IEEE Trans. Comput. Aided Des. 10 (5) (1991) 652-667.
    • (1991) IEEE Trans. Comput. Aided Des. , vol.10 , Issue.5 , pp. 652-667
    • Ghosh, A.1    Devadas, S.2    Newton, A.R.3
  • 22
  • 23
  • 24
    • 0008128895 scopus 로고
    • An automatic test pattern generator for large sequential circuits based on genetic algorithm
    • October
    • P. Prineto, M. Rebaudengo, M.S. Reorda, An automatic test pattern generator for large sequential circuits based on genetic algorithm, Proc. Int. Test. Conf., October 1994, pp. 240-249.
    • (1994) Proc. Int. Test. Conf. , pp. 240-249
    • Prineto, P.1    Rebaudengo, M.2    Reorda, M.S.3
  • 30
    • 0029223036 scopus 로고
    • Combining deterministic and genetic approaches for sequential circuit test generation
    • June
    • E.M. Rudnick, J.H. Patel, Combining deterministic and genetic approaches for sequential circuit test generation, Proc. 32nd Design Automation Conf., June 1995, pp. 183-188.
    • (1995) Proc. 32nd Design Automation Conf. , pp. 183-188
    • Rudnick, E.M.1    Patel, J.H.2
  • 31
    • 0028706754 scopus 로고
    • Iterative[Simulation-Based Genetics + Deterministic Techniques] = com-plete ATPG
    • November
    • D.G. Saab, Y.G. Saab, J.A. Agraham, Iterative[Simulation-Based Genetics + Deterministic Techniques] = com-plete ATPG, Dig. Int. Conf. On Computer-Aided Design, November 1994, pp. 40-43.
    • (1994) Dig. Int. Conf. on Computer-Aided Design , pp. 40-43
    • Saab, D.G.1    Saab, Y.G.2    Agraham, J.A.3
  • 32
    • 0026867440 scopus 로고
    • The multiple observation time teset strategy
    • I. Pomeranz, S.M. Reddy, The multiple observation time teset strategy, IEEE Trans. Comput. 41 (5) (1992) 627-637.
    • (1992) IEEE Trans. Comput. , vol.41 , Issue.5 , pp. 627-637
    • Pomeranz, I.1    Reddy, S.M.2
  • 33
    • 0004602745 scopus 로고
    • Fault simulation for synchronous sequential circuits under the multiple observation time testing approach
    • I. Pomeranz, S.M. Reddy, fault simulation for synchronous sequential circuits under the multiple observation time testing approach, European Testing Conf., 1993, pp. 292-300.
    • (1993) European Testing Conf. , pp. 292-300
    • Pomeranz, I.1    Reddy, S.M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.