Timing verification of sequential logic circuits based on controlled multi-clock path analysis

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E81-A, Issue 12, 1998, Pages 2515-2520

  Nakamura, Kazuhiro ^a   Kimura, Shinji ^a   Takagi, Kazuyoshi ^a   Watanabe, Katsumasa ^a  

^a NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

Author keywords

False path; Maximum delay analysis; Multiple clock operation; Timing verification

Indexed keywords

ELECTRIC NETWORK ANALYSIS; OPTIMIZATION; TIMING CIRCUITS;

CONTROLLED MULTI-CLOCK PATH ANALYSIS; MAXIMUM DELAY ANALYSIS; TIMING VERIFICATION;

SEQUENTIAL CIRCUITS;

EID: 0032305823     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (8)

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