Exploiting Multicycle False Paths in the Performance Optimization of Sequential Logic Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 14, Issue 9, 1995, Pages 1067-1075

  Ashar, Pranav ^a   Dey, Sujit ^a   Malik, Sharad ^b  

^a NEC LABORATORIES AMERICA   (United States)

^b PRINCETON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; COMPUTER AIDED DESIGN; ELECTRIC NETWORK SYNTHESIS; LOGIC GATES; OPTIMIZATION; PERFORMANCE; TRIGGER CIRCUITS;

MULTICYCLE FALSE PATHS; PERFORMANCE OPTIMIZATION; SEQUENTIAL LOGIC CIRCUITS;

SEQUENTIAL CIRCUITS;

EID: 0029373038     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.406708     Document Type: Article

References (19)

1. F. Brglez, D. Bryan, and K. Kozminski, “Combinational profiles of sequential benchmark circuits,” in Proc. Int. Symp. Circuits Syst., Portland, OR, May 1989.
2. H. C. Chen and D. H. Du, “Path sensitization in circuit path problem,” IEEE Trans. Computer-Aided Design, vol. 12, no. 2, pp. 196–207, Feb. 1993.
3. K.-C. Chen and M. Fujita, “Network resynthesis for delay minimization,” in Proc. Design Automation Conf., June 1992, pp. 443–448.
4. G. DeMicheli, “Synchronous logic synthesis: Algorithms for cycle-time minimization,” IEEE Trans. Computer-Aided Design, vol. 10, no. 1, pp. 63–73, Jan. 1991.
5. S. Devadas, K. Keutzer, and S. Malik, “Delay computation in combinational circuits: Theory and algorithms,” in Proc. Int. Conf. Computer-Aided Design, Nov. 1991, pp. 176–179.
6. J. P. Fishburn and A. E. Dunlop, “TILOS: A posinomial programming approach to transistor sizing,” in Proc. Int. Conf. Computer-Aided Design, Nov. 1985, pp. 326–328.
7. A. Ghosh, S. Devadas, and A. R. Newton, “Test generation for highly sequential circuits,” in Proc. Int. Conf. Computer-Aided Design, Nov. 1989, pp. 362–365.
8. K. Keutzer, S. Malik, and A. Saldanha, “Is redundancy necessary to reduce delay?” IEEE Trans. Computer-Aided Design, vol. 10, no. 4, pp. 427–435, Apr. 1991.
9. C. E. Leiserson and J. B. Saxe, “Retiming synchronous circuitry,” Algorithmica, vol. 6, no. 1, pp. 5–36, 1991.
10. R. Lisanke, Ed., FSM Benchmark Suite. Research Triangle Park, NC: Microelectronics Center of North Carolina, 1987.
11. S. Malik, E. Sentovich, R. K. Brayton, and A. Sangiovanni-Vincentelli, “Retiming and resynthesis: Optimizing sequential networks with combinational techniques,” IEEE Trans. Computer-Aided Design, vol. 10, no. 1, pp. 74–84, Jan. 1991.
12. S. Malik, K. J. Singh, R. K. Brayton, and A. Sangiovanni-Vincentelli, “Performance optimization of pipelined circuits,” in Proc. Int. Conf. Computer-Aided Design, Nov. 1990, pp. 410–413.
13. P. C. McGeer and R. K. Brayton, Integrating Functional and Temporal Domains in Logic Design. Norwell, MA: Kluwer, 1991.
14. A. Saldanha, R. K. Brayton, and A. Sangiovanni-Vincentelli, “Circuit structure relations to redundancy and delay: The KMS algorithm revisited,” in Proc. Design Automation Conf., June 1992, pp. 245–252.
15. E. M. Sentovich, K. J. Singh, C. Moon, H. Savoj, R. K. Brayton, and A. Sangiovanni-Vincentelli, “Sequential circuit design using synthesis and optimization,” in Proc. Int. Conf. Computer Design, 1992, pp. 328–333.
16. K. J. Singh, A. Wang, R. K. Brayton, and A. Sangiovanni-Vincentelli, “Timing optimization of combinational logic,” in Proc. Int. Conf. Computer-Aided Design, Nov. 1988, pp. 282–285.
17. H. Touati and R. K. Brayton, “Computing initial states of retimed circuits,” IEEE Trans. Computer-Aided Design, vol. 12, no. 1, pp. 157–162, Jan. 1993.
18. H. Touati, C. Moon, R. K. Brayton, and A. Wang, “Performance-oriented technology mapping,” in Proc. Sixth MIT VLSI Conf., Apr. 1990, pp. 79–97.
19. H. Touati, H. Savoj, B. Lin, R. K. Brayton, and A. Sangiovanni-Vincentelli, “Implicit state enumeration of finite state machines using BDDs,” in Proc. Int. Conf. Computer-Aided Design, Nov. 1990, pp. 130–133.