Timing verification using statically sensitizable paths

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 9, Issue 10, 1990, Pages 1073-1084

  Benkoski, Jacques ^a   Vanden Meersch, Erik ^a   Claesen, Luc J M ^a   De Man, Hugo ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

DATA PROCESSING - PERT; MATHEMATICAL TECHNIQUES - ALGORITHMS;

FALSE PATH PROBLEM; TIMING VERIFICATION;

LOGIC CIRCUITS;

EID: 0025505723     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (16)