BIST scheme for asynchronous logic

Proceedings of the Asian Test Symposium

Volumn , Issue , 1998, Pages 27-32

  Alves, Vladimir C ^a   Franca, Felipe M G ^a   Granja, Edson P ^a  

^a FEDERAL UNIVERSITY OF RIO DE JANEIRO   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

DISTRIBUTED SYNCHRONIZERS; SCHEDULING BY EDGE REVERSAL (SER);

ASYNCHRONOUS SEQUENTIAL LOGIC; ELECTRIC FAULT LOCATION; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK TOPOLOGY; LOGIC CIRCUITS;

BUILT-IN SELF TEST;

EID: 0032295569     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

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