Low-power globally asynchronous locally synchronous design using self-timed circuit technology

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 1997, Pages 1808-1811

  Jou, Shyh Jye ^a   Chuang, I Yao ^a  

^a NATIONAL CENTRAL UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; COMPUTER ARCHITECTURE; COMPUTER HARDWARE;

GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS (GALS) DESIGN TECHNIQUE; SELF TIMED CIRCUIT;

TIMING CIRCUITS;

EID: 0030719807     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)