Efficient clocking of a Wave-domino pipeline

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 1997, Pages 1832-1835

  Matthew, Sanu ^a   Sridhar, Ramalingam ^a  

^a UNIVERSITY AT BUFFALO   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL CIRCUITS; ELECTRIC CLOCKS; LOGIC CIRCUITS;

WAVE DOMINO PIPELINE;

PIPELINE PROCESSING SYSTEMS;

EID: 0030685347     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)