Sequential modeling of via geometry in photosensitive MCM dielectric materials using neural networks

Proceedings - 4th International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces

Volumn 1998-March, Issue , 1998, Pages 93-99

  Kim, Tae Seon ^a   May, Gary S ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC MATERIALS; ELECTRONICS PACKAGING; INTERFACES (MATERIALS); LIGHT SENSITIVE MATERIALS; OPTIMIZATION; PACKAGING MATERIALS; PHOTOSENSITIVITY; SUBSTRATES; FABRICATION; MATHEMATICAL MODELS; MULTICHIP MODULES; NEURAL NETWORKS; ORGANIC POLYMERS; PROCESS CONTROL;

DESIGNED EXPERIMENTS; LOW COST MANUFACTURING; MODELING STRUCTURES; OPTIMIZATION AND CONTROL; PHOTOSENSITIVE POLYMERS; PREDICTION CAPABILITY; SEQUENTIAL METHODS; SEQUENTIAL NEURAL NETWORKS;

PROCESS CONTROL; ELECTRONICS PACKAGING;

DEPOSITED MULTICHIP MODULES TECHNOLOGY; LAMINATED MULTICHIP MODULES TECHNOLOGY; PHOTOSENSITIVE BENZOCYCLOBUTENE; VIA FORMATION;

EID: 0032230579     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISAPM.1998.664441     Document Type: Conference Paper

References (11)

1. L. Higgins and D. Robinson, "Development and Assembly of a 40 MHz MCM-L Based DSP-Fast Static RAM Multichip Module," Proceedings of ICEMM, Denver, CO, pp. 563-574, April, 1993.
2. T. Shimoto, K. Matsui and K. Utsumi, "CuPhotosensitive-BCB Thin-Film Multilayer Technology for High-Performance Multichip Modules, " IEEE Trans. Comp., Pack., Manufac. Tech., Part B, vol. 18, no. 1, Feb., 1995.
3. P. Garrou, R. Heistand, M. Dibbs, T. Manial, C. Mohler, T. Stokich, P. Townsend, G. Adema, M. Berry, and I. Turlik, "Rapid Thermal Curing of BCB Dielectric," IEEE Trans. CHMT, vol. 16, no. 1, pp. 46-51, February, 1993.
4. T. Kim and G. May, "Modeling of Via Formation by Photosensitive Dielectric Materials for MCM Applications," Proc. 5" Internat'l Conf. On Prop. & Appli. Of Dielectric Mat., pp. 930-934, May, 1997
5. G. May, "Manufacturing ICs The Neural Way", IEEE Spectrum, vol. 31, no. 9, pp. 47-51, September, 1994.
6. S. Leang and C. Spanos, "A Novel In-Line Automated Metrology for Photolithography, " IEEE Trans. Semi. Manufac., vol. 9, no. 1, February, 1996.
7. R. Tummala and E. Rymaszewski, Microelectronics Packaging Handbook, Van Nostard Reinhold, New York, 1989.
8. P. Garrou, "Polymer Dielectrics for Multichip Module Packaging," Proceeding of the IEEE, vo1.80, no.12, pp. 1942-1954, December, 1992.
9. G. Box, W. Hunter, and J. Hunter, Statistics fur Experimenters, New York Wiley, 1978.
10. G. Cardarelli, M. Palumdo, and P. Pelagagge, "Photolithography Process Modeling Using Neural Networks," Semiconductor International, vol. 19, no.6, pp. 199-206, June, 1996.
11. C. Himmel and G. May, "Advantages of Plasma Etch Modeling Using Neural Networks Over Statistical Techniques," IEEE Trans. Semi. Manufac., vol. 6, no. 2, pp. 10103-111, May, 1993.