Area-speed tradeoffs for hierarchical field-programmable gate arrays

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 1996, Pages 51-57

  Chan, Vi Cuong ^a   Lewis, David M ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED LOGIC DESIGN; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; DIGITAL CIRCUITS; HIERARCHICAL SYSTEMS; LOGIC GATES; TABLE LOOKUP;

AREA SPEED TRADE OFFS; BENCHMARK CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS; ROUTING CHANNEL REQUIREMENTS; TIMING PERFORMANCE MEASUREMENT;

LOGIC CIRCUITS;

EID: 0029714355     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/228370.228378     Document Type: Conference Paper

References (21)