Development of single-chip multi-GB/s DRAMs

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 40, Issue , 1997, Pages 226-227

  Crisp, Richard ^a   Donnelly, Kevin ^a   Moncayo, Alfredo ^a   Perino, Don ^a   Zerbe, Jared ^a  

^a RAMBUS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; BUFFER STORAGE; DATA HANDLING; ELECTRONICS PACKAGING; ERROR CORRECTION; INTERFACES (COMPUTER); TIMING CIRCUITS;

BIMODAL JITTER; DATA RATES; DYNAMIC RANDOM ACCESS MEMORY (DRAM); LATENCY;

RANDOM ACCESS STORAGE;

EID: 0031070401     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)