A configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generator

IEEE Journal of Solid-State Circuits

Volumn 33, Issue 11, 1998, Pages 1752-1757

  Yabe, Tomoaki ^a   Miyano, Shinji ^a   Sato, Katsuhiko ^a   Wada, Masaharu ^a   Haga, Ryo ^a   Wada, Osamu ^a   Enkaku, Motohiro ^a   Hojyo, Takehiko ^a   Mimoto, Kenichiro ^a   Tazawa, Masaaki ^a   Ohkubo, Tsutomu ^a   Numata, Kenji ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

DRAM; DRAM ASIC; DRAM macro; Embedded DRAM; Memory generator

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; STORAGE ALLOCATION (COMPUTER);

MEMORY GENERATORS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0032202488     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.726570     Document Type: Article

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