Wide-area clock distribution using controlled delay lines

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 2, Issue , 1998, Pages 63-66

  Aguiar, Rui L ^a   Santos, Dinis M ^a  

^a UNIVERSITY OF AVEIRO   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS INDUSTRY; COMPUTER SIMULATION; ELECTRIC DELAY LINES; MULTICHIP MODULES; OBJECT ORIENTED PROGRAMMING; VLSI CIRCUITS; WSI CIRCUITS;

CLOCK DISTRIBUTION; PHASE ACCURACY; PHASE AMBIGUITY; SUB NANOSECONDS; WAFER SIZES;

CLOCKS; INTEGRATED CIRCUIT LAYOUT;

CLOCK DISTRIBUTION; DELAY LOCKED LOOPS (DLL);

EID: 0032281532     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.1998.814825     Document Type: Conference Paper

References (8)

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