Low-power coefficient segmentation algorithm for FIR filter implementation

Electronics Letters

Volumn 34, Issue 19, 1998, Pages 1817-1819

  Erdogan, A T ^a   Arslan, T ^a  

^a CARDIFF UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CAPACITANCE; CMOS INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; HEURISTIC METHODS; MULTIPLYING CIRCUITS;

MULTIPLICATION ALGORITHMS;

FIR FILTERS;

EID: 0032164278     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19981290     Document Type: Article

References (6)

1. ERDOGAN, A.T., and ARSLAN, T.: 'Low power multiplication scheme for FIR filter implementation on single multiplier CMOS DSP processors', Electron. Lett., 1996, 32, (21), pp. 1959-1960
2. CHANDRAKASAN, A.P., and BRODERSEN, R.W.: 'Minimising power consumption in digital CMOS circuits', Proc. IEEE, 1995, 83, (4), pp. 498-523
3. SU, C.-L., TSUI, C.-Y., and DESPAIN, A.M.: 'Low power architecture design and compilation techniques for high performance processors'. IEEE COMPCON 94, 1994, pp. 489-498
4. BRIGHT, M.S., and ARSLAN, A.: 'A genetic framework for the high-level optimisation of low power VLSI DSP systems', Electron. Lett., 1996, 32, (13), pp. 1150-1151
5. CHANDRAKASAN, A.P., POTKONJAK, M., MEHRA, R., RABAEY, J., and BRODERSEN, R.W.: 'Optimizing power using transformations', IEEE Trans., 1995, CAD-14, (1), pp. 12-31
6. THOMAS. D.E., and MORBY, P.R.: 'The Verilog hardware description language' (Kluwer Academic Publishers, 1995)