Genetic framework for the high level optimisation of low power VLSI DSP systems

Electronics Letters

Volumn 32, Issue 13, 1996, Pages 1150-1151

  Bright, M S ^a   Arslan, T ^a  

^a CARDIFF UNIVERSITY   (United Kingdom)

Author keywords

Digital signal processing; Genetic algorithms; VLSI

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL FILTERS; DIGITAL SIGNAL PROCESSING; ELECTRIC POWER SUPPLIES TO APPARATUS; GENETIC ALGORITHMS; MATHEMATICAL TRANSFORMATIONS; OPTIMIZATION;

AVENHAUS FILTER; HIGH LEVEL TRANSFORMATIONS; POWER CONSUMPTION;

VLSI CIRCUITS;

EID: 0030166470     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19960795     Document Type: Article

References (11)

1. SING, D., RABAEY, M., PEDRAM, M., CATTHOOR, F., RAJGOPAL, S., SEHGAL, N., and MOZDZEN, T.J.: 'Power conscious CAD tools and methodologies : A perspective', Proc. IEEE, 1995, 83, (4), pp. 570-594
2. CHANDRAKASAN, A.P., SHENO, S., and BRODERSON, R.W.: 'Low-power CMOS digital design', IEEE J. Solid-State Circuits, 1992, SSC-27, (4), pp. 473-484
3. CHANDRAKASAN, A.P., and BRODERSON, R.W.: 'Minimising power consumption in digital CMOS circuits', Proc. IEEE, 1995, 83, (4), pp. 498-523
4. ARSLAN, T., ERDOGAN, A.T., and HORROCKS, D.H.: 'Low power design for DSP: Methodologies and techniques', Microelectron. J., (to be published)
5. CHANDRAKASAN, A.P., POTKONJAK, M., MEHRA, R., RABAEY, J., and BRODERSON, R.W.: 'Optimising power using transformations', IEEE Trans. Comput. Aid. Des. Integr. Circuits Syst., 14, (4), pp. 12-30
6. DAVIS, L., 'Handbook of genetic algorithms' (Van Nostrand Reinhold, New York, 1991)
7. ARSLAN, T., HORROCKS, D.H., and OZDEMIR, E.: 'Structural cell-based VLSI circuit design using a genetic algorithm'. Int. Symp. Circuits Syst., Atlanta, USA, 1996. (accepted, to be presented)
8. O'DARE, M.J., and ARSLAN, T.: 'Generating test patterns for VLSI circuits using a genetic algorithm', Electron. Lett., 1994, 30, (10), pp. 778-779
9. LUCKE, L.E., and PARHI, K.K.: 'High-level algorithm and architecture transformations for DSP synthesis', J. VLSI Signal Process., 1995, 9, pp. 121-143
10. PARHI, K.K.: 'Static rate-optimal scheduling of iterative data-flow programs via optimum unfolding', IEEE Trans. Comput., 1991, 40, (2), pp. 178-195
11. HUANG, S., and RABAEY, J.: 'Maximising the throughput of high performance DSP applications using behavioural transformations'. Proc. EDAC-ETC-EUROASIC '94, Paris, France, March 1994, pp. 25-30