Low power multiplication scheme for FIR filter implementation on single multiplier CMOS DSP processors

Electronics Letters

Volumn 32, Issue 21, 1996, Pages 1959-1960

  Erdogan, A T ^a   Arslan, T ^a  

^a CARDIFF UNIVERSITY   (United Kingdom)

Author keywords

CMOS integrated circuits; Digital signal processing; FIR filters

Indexed keywords

ALGORITHMS; CALCULATIONS; CAPACITANCE; COMPUTER SIMULATION; DIGITAL FILTERS; DIGITAL SIGNAL PROCESSING; FREQUENCY MULTIPLYING CIRCUITS; LOGIC GATES; PROBABILITY; SWITCHING;

MULTIPLIER ACCUMULATOR; POWER DISSIPATION; POWER OPTIMIZATION; PRE CALCULATED VALUE MEMORY; PRE CALCULATED VALUES; WORDLENGTHS;

CMOS INTEGRATED CIRCUITS;

EID: 0030262410     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19961298     Document Type: Article

References (7)

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5. MITRA, S.K., and KAISER, J.F: 'Handbook for digital signal processing' (Wiley Interscience Publication, New York, 1993)
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