Design Approaches to Field-Programmable Analog Integrated Circuits

Analog Integrated Circuits and Signal Processing

Volumn 17, Issue 1-2, 1998, Pages 7-34

  D'Mello, Dean R ^a,b,c,d   Gulak, P Glenn ^a,e,f,g  

^a UNIVERSITY OF TORONTO   (Canada)

^b LSI Corporation Canada   (Canada)

^c IBM CANADA LTD   (Canada)

^d Celestica Inc   (Canada)

^e IEEE

^f UNIVERSITY OF MANITOBA   (Canada)

^g Stanford University   (United States)

Author keywords

Analog CAD; Field programmable; FPAA; FPGA; FPMA; IC; Mixed signal IC; Programmable analog

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER SOFTWARE; ELECTRONIC EQUIPMENT; TECHNOLOGY;

FIELD-PROGRAMMABLE ANALOG;

INTEGRATED CIRCUITS;

EID: 0032157832     PISSN: 09251030     EISSN: None     Source Type: Journal    
DOI: 10.1007/978-1-4757-5224-3_1     Document Type: Article

References (91)

1. M. Ismail and S. Bibyk, "CAD Latches Onto New Techniques for Analog ICs." IEEE Circuits and Devices Magazine, September 1991, pp. 11-17.
2. W. J. McClean, ed., "Status 1996, A Report on the Integrated Circuit Industry." Integrated Circuit Engineering Corp., 1996.
3. A. Bratt and I. Macbeth, "Design and Implementation of a FPAA.", ACM/SIGDA FPGA'96, Monterey, Ca., Feb. 11-13, 1996, pp. 88-93.
4. H. Kutuk and S. Kang, "A Field-Programmable Analog Array (FPAA) Using Switched-Capacitor Techniques." IEEE ISCAS 1996 3, pp. 41-44.
5. D. Vallancourt and Y. P. Tsividis, "Timing-Controlled Switched Analog Filters with Full Digital Programmability." IEEE ISCAS 1987, pp. 329-333.
6. Adaptive Logic, AL220 Analog Micro Controller preliminary data sheet, WWW site: http://www.adaptivelogic.com
7. S. T. Chang, B. R. Hayes-Gill, and C. J. Paull, "Multi-Function Block for a Switched Current Field Programmable Analog Array." Midwest Symposium on Circuits and Systems, Ames, Iowa, August 18-21 1996.
8. E. Lee and P. G. Gulak, "Field-Programmable Analogue Array based on MOSFET Transconductors." Electronic Letters 28(1), pp. 28-29, January 2, 1992.
9. S. Chang, B. Hayes-Gill, and C. Paull, "Implementation of a Multi-Function Signal Detection Block for a Field-Programmable Analogue Array." Fifth Eurochip Workshop on VLSI Design Training, Oct. 17-19, 1994, Dresden, Germany, pp. 226-231.
10. E. Pierzchala, M. Perkowski, Paul Van Halen, and Rolf Schaumann, "Current-Mode Amplifier-Integrator for a Field-Programmable Analog Array." ISSCC Digest of Technical Papers, Feb. 1995, pp. 196-197.
11. C. Premont, R. Grisel, N. Abouchi, and J Chante, "Current-Conveyor Based Field Programmable Analog Array." Midwest Symposium on Circuits and Systems, Ames, Iowa, August 18-21 1996.
12. S. H. K. Embabi, X. Quan, N. Oki, A. Manjrekar, and E. Sánchez-Sinencio, "A Field Programmable Analog Signal Processing Array." Midwest Symposium on Circuits and Systems, Ames, Iowa, August 18-21 1996.
13. H.W. Klein, "The EPAC Architecture: An Expert Cell Approach to Field Programmable Analog Devices." ACM/ SIGDA FPGA'96, Monterey, CA, Feb. 11-13, 1996, pp. 94-98.
14. C. Toumazou and J. Lidgely, "Universal Current-Mode Analogue Amplifiers." In Analogue IC Design: the Current-Mode Approach, Peter Peregrinus Ltd., London, UK, 1990, pp. 127-180.
15. G. Roberts, "Generalization and Application of the Intermediate Function Technique." PhD. Dissertation, University of Toronto, 1989.
16. E. Lee and P. G. Gulak, "Prototype Design of a Field-Programmable Analog Array." in Proceedings of CCVLSI 1990, Ottawa, Canada, October 21-23, 1990.
17. C. Toumazou, J. B. Hughes, and N. C. Battersby eds., Switched-Currents an Analogue Technique for Digital Technology, Peter Peregrinus: UK, 1993.
18. E. Lee, "Field-Programmable Analog Arrays Based on MOS Transconductors." PhD. dissertation, University of Toronto, 1995.
19. M. Sivilotti, "A Dynamically Configurable Architecture for Prototyping Analog Circuits." MIT VLSI Conference, 1988, pp. 237-258.
20. W. A. Fisher, R. J. Fujimoto, and R. C. Simpson, "A Programmable Analog Neural Network Processor." IEEE Transactions on Neural Networks 2(2), pp. 222-228, March 1991.
21. K. Austin, "Integrated Circuit for Analogue System." U.S. Patent 5,196,740, Pilkington Micro-Electronics, March 23, 1993.
22. Analog Devices, "Low-Noise, 90MHz Variable-Gain Amplifier." AD603 Data Sheet, 1995.
23. Burr-Brown, "Digitally-Controlled Programmable-Gain Instrumentation Amplifier." PGA200/201 Data Sheet, 1987.
24. Burr-Brown, "Universal Active Filter." UAF42, Data Sheet, 1990.
25. F. Goodenough, "Voltage-Tunable Linear Filters Move onto a Chip." Electronic Design, February 8, 1990.
26. F. J. Kub, I. A. Mack, K. K. Moon, C. T. Yao, and J. A. Modolo, "Programmable Analog Synapses for Microelectronic Neural Networks using a Hybrid Digital-Analog Approach." presented at the IEEE International Conference on Neural Networks, San Diego, CA, July 24-27, 1988.
27. F. J. Kub, K. K. Moon, I. A. Mack, and F. M. Long, "Programmable Analog Vector-Matrix Multipliers." IEEE Journal of Solid State Circuits 25(1), pp. 207-214, February 1990.
28. S. Satyanarayana, Y. P. Tsividis, and H. P. Graf, "A Reconfigurable VLSI Neural Network." IEEE Journal of Solid State Circuits 27(1), pp. 67-81, January 1992.
29. E. Lee and P. G. Gulak, "Error Correction Technique for Multivalued MOS Memory." Electronics Letters 27(15), pp. 1321-1323, July 18, 1991.
30. E. Lee and P. G. Gulak, "Current-Mode Multivalued Dynamic MOS Memory with Error Correction." Electronics Letters 28(11), pp. 1067-1069, May 21, 1992.
31. Pilkington Micro-electronics Limited (PMeL) WWW site: http://www.pmel.com.
32. IMP Inc., "Programmable Analog Signal-Conditioning Circuit." IMP50E10 and IMP50E30 Data sheets, 1994.
33. T. Roiné, "The FPAA Interface, manual and report" Technical Report, University of Toronto, December 1995.
34. S. Lecler, "The FPAA Programming Tool, manual and report." Technical Report, University of Toronto, 1994.
35. R. A. Saleh, D. L. Rhodes, E. Christen, and B. A. A. Antao, "Analog Hardware Description Languages." IEEE Custom Integrated Circuits Conference 1994, pp. 349-356.
36. WWW site for the IEEE VHDL-A standard, http://vhdl.org/vi/ analog/.
37. J. Bergé, O. Levia, and J. Rouillard eds., Modeling in Analog Design, Kluwer Academic Publishers: The Netherlands, 1995.
38. A. F. Arbel, "Current Operated Nucleonic Modules." Nuclear Instruments and Methods 32, pp. 341-346, 1965.
39. R. Joetten, T Web, J. Wolters, H. Ring, and B. Bjoernsson, "A New Real-Time Simulator for Power System Studies." IEEE Transactions on Power Apparatus and Systems PAS-104(9), pp. 2604-2611, September 1985.
40. F. Goodenough, "Analog Arrays Rival Digital Designs in Facility, Performance." Electronic Design pp. 86-96, June 13, 1985.
41. G. Gianella, "Array IC Presents New Ways to Customize Analog Circuits Without Wasting Silicon." Electronic Design pp. 171-178, May 1, 1986.
42. L. B. Wheaton, "Universal Cell for Bipolar NPN and PNP Transistors and Resistive Elements." U.S. Patent 5,021,856, Plessey Overseas Limited, June 4, 1991.
43. K. Negus, R. Koupal, D. Millicker, and C. Snapp, "Silicon Bipolar Mixed-Signal Parameterized-Cell Array for Wireless Applications to 4GHz.", ISSCC Digest of Technical Papers, San Francisco, CA, pp. 230-231, 1992.
44. P. P. Duchene, M. J. Declerq, B. Goffart, and M. Novak, "Analog Circuit Implementation on CMOS Semi-Custom Arrays." IEEE Journal of Solid-State Circuits 28(7), pp. 872-874, July 1993.
45. S. Shinbara, "Analog Standard Cell." U.S. Patent 5,302,864, Kabushiki Kaisha Toshiba, April 12, 1994.
46. S. L. Wong, S. Venkitasubrahmanian, M. J. Kim, and J. C. Young, "Design of a 60-V 10-A Intelligent Power Switch Using Standard Cells." IEEE Journal of Solid State Circuits 27(3), pp. 429-432, March 1993.
47. M. Soyuer, J. N. Burghartz, K. A. Jenkins, H. A. Ainspan, and F. J. Canora, "RF and Microwave Building Blocks in a Standard BiCMOS Technology." IEEE ISCAS 1996, 4, pp. 89-92.
48. R. C. Chang, B. J. Sheu, J. Choi, and D. C-H Chen, "Programmable Weight Building Blocks for Analog VLSI Neural Network Processors." Analog Integrated Circuits and Signal Processing 9(3), pp. 215-230, April 1996.
49. J. Van der Spiegel, P. Mueller, D. Blackman, P. Chance, C. Donham, R. Etienne-Cummings, and Peter Kinget, "An Analog Neural Computer with Modular Architecture for Real-Time Dynamic Computations." IEEE Journal of Solid State Circuits 27(1), pp. 82-92, January 1992.
50. S. Eberhardt, T. Duong, and A. Thakoor, "Design of Parallel Hardware Neural Network Systems from Custom Analog VLSI 'Building Block' Chips." IEEE INNS Intl. Joint Conference on Neural Networks 2, pp. 183-190, June 1989.
51. B. J. Sheu, "VLSI Neurocomputing with Analog Programmable Chips and Digital Systolic Array Chips." Proc. IEEE ISCAS 1991, pp. 1267-1270.
52. E. Lee and G. Gulak, "ACMOS Field-Programmable Analog Array." ISSCC Digest of Technical Papers, Feb. 1991, pp. 186-188.
53. E. Lee and G. Gulak, "A Transconductor-Based Field-Programmable Analog Array." ISSCC Digest of Technical Papers, Feb. 1995, pp. 198-199.
54. L. O. Chua and L. Yang, "Cellular Neural Networks: Theory and Applications." IEEE Transactions on Circuits and Systems 35(10), pp. 1257-1290, October 1988.
55. P. Kinget and M. S. J. Steyaert, "A Programmable Analog Cellular Neural Network CMOS Chip for High Speed Image Processing." IEEE Journal of Solid-State Circuits 30(3), March 1995.
56. P. Kinget and M. Steyaert, "An Analog Parallel Array Processor for Real-Time Sensor Signal Conditioning." IEEE ISSSCC Digest of Technical Papers, Feb. 1996, pp. 92-93.
57. T. Roska and L.O. Chua, "The CNN Universal Machine: An Analogic Array Computer." IEEE Transactions on Circuits and Systems II 40(3), pp. 163-173, March 1993.
58. H. C. Anderson, "Complex Signal Transformation Using a Resistive Network." U.S. Patent 5,058,049, Motorola Inc., October 15, 1991.
59. E. Lee and G. Gulak, "A CMOS Field-Programmable Analog Array." IEEE Journal of Solid-State Circuits 26(12), pp. 1860-1867, December 1991.
60. D. Vallancourt and Y. P. Tsividis, "Timing-Controlled Fully Programmable Analog Signal Processors Using Switched Continuous-Time Filters." IEEE Transactions on Circuits and Systems 35(8), pp. 947-954, August 1988.
61. Pilkington Micro-Electronics, "Programmable Switched Capacitor Circuit." UK Patent Application GB 2,275,144A, 17/08/1994.
62. P. Clarke, "Analog-cell IC takes reconfigurable tack." Electronic Engineering Times, October 7, 1996, p. 1.
63. P. Clarke, "Moto buys Pilkington, gets programmable logic." Electronic Engineering Times, March 24, 1997, p. 18.
64. Z. Czarnul, "Novel MOS Resistive Circuit for Synthesis of Fully-Integrated Continuous-Time Filters." IEEE Trans. Circuits Syst., CAS-33, pp. 718-722, July 1986.
65. E. Pierzchala, M. A. Perkowski, and S. Grygiel, "A Field-Programmable Analog Array for Continuous, Fuzzy, and Multi-Valued Logic Applications." IEEE ISMVL, Boston, Mass., May 1994, pp. 148-155.
66. P. Chow, P. Chow, and P.G. Gulak, "A Field-Programmable Mixed Analog-Digital Array." ACMISIGDA FPGA'95, Monterey, CA, Feb. 12-14, 1995, pp. 104-109.
67. P. Chow, S. O. Seo, K. Chung, G. Paez, and J. Rose, "A High-Speed FPGA Using Programmable Mini-tiles." Proc. 1993 Symposium of Integrated Systems, March 1993.
68. K. Bult and G. Geelen, "An Inherently Linear and Compact MOST-Only Current-Division Technique." IEEE JSSC 27(12), pp. 1730-1735, December 1992.
69. C. Zhang, A. Bratt, and I. Macbeth, "A New Field Programmable Mixed Signal Array and its Application." 4th Canadian Workshop on Field-Programmable Devices, May 13-14, 1996, Toronto, Canada.
70. P. Clarke and R. Wilson, "Pilkington Details its Analog-Array Effort." Electronic Engineering Times, September 25, 1995, p. 4.
71. J Faura, C. Horton, P. van Duong, J Madrenas, M. A. Aguirre, and J. M. Insenser, "A Novel Mixed Signal Programmable Device with On-chip Microprocessor." IEEE Custom Integrated Circuits Conference 1997.
72. Precision Monolithics Inc., "Analog Signal Processing Subsystem." GAP-01 Data Sheet, 1982.
73. P. Henneuse, "Low Glitch Current Switch." U.S. Patent 4,285,051, Precision Monolithics Inc., August 18, 1981.
74. Xicor, "Nonvolatile Digital Potentiometer." X9C102 Data Sheet, 1994.
75. Analog Devices, "2-/4-Channel Digital Potentiometer." AD8402/8403 Data Sheet, 1995, WWW site: http://www.analog.com
76. Texas Instruments, TLC3203X/4X Data Sheet, 1994, WWW site: http://www.ti.com.
77. F. Goodenough, "Analog Counterparts of FPGAs Ease System Design." Electronic Design, Oct. 14, 1994, pp. 63-73.
78. Zetex Semiconductors WWW site: http://www.zetex.com.
79. R. W. Harris and H. T. Lee, "Digitally Controlled Variable Conductance." U.S. Patent 4,009,400, Lockheed Missiles and Space Company Inc., February 22, 1977.
80. Z. Czarnul, "Semiconductive MOS Resistance Network." U.S. Patent 4,710,726, Columbia University, December 1, 1987.
81. N. Sako, "Integrated Circuit and Gate Array." U.S. Patent 5,298,806, Kawasaki Steel Corp., March 29, 1994.
82. K. A. El-Ayat, "Mixed Mode Analog/Digital Programmable Interconnect Architecture." U.S. Patent 5,107,146, Actel Corporation, April 21, 1992.
83. O. Agrawal, M. Wright, and S. Sidman, "Programmable Logic Device Incorporating Voltage Comparator." U.S. Patent 5,153,462, Advanced Micro Devices, Oct. 6, 1992.
84. O. Agrawal and M. Wright, "Programmable Logic Device Incorporating Digital-to-Analog Converter." U.S. Patent 5,191,242, Advanced Micro Devices, March 2, 1993.
85. R. A. Baumgartner and E. C. Herleikson, "Signal Processing Circuits with Digital Programmability." U.S. Patent 5,337,230, Hewlett-Packard Company, August 9, 1994.
86. R. Ananth, "Signal Processing Structures for Power-Supervisory and Low-Frequency Applications." MASc. Thesis, University of Toronto, 1992.
87. S. R. Zarabadi, F. Larsen, and M. Ismail, "A Reconfigurable Op-Amp/DDA CMOS Amplifier Architecture." IEEE Trans. Ccts & Sys.-I: Analog and Digital Sig. Proc. 39(6), June 1992.
88. A. Sheikholeslami, P. G. Gulak, and T. Hanyu, "A Multiple-Valued Ferrolectric ContentAddressable Memory." IEEE ISMVL, Santiago de Compostela, Spain, May 1996.
89. M. J. Wirthlin and B. L. Hutchings, "Sequencing Run-Time Reconfigured Hardware with Software." ACM/SIGDA FPGA'96, Monterey, Ca., Feb. 11-13, 1996, pp. 122-128.
90. Xilinx Inc., "XC6200 Field-Programmable Gate Arrays." Data Sheet, 1996, WWW site: http://www.xilinx.com
91. E. K. F. Lee, "Reconfigurable Pipelined Data Converter Architecture." Midwest Symposium on Circuits and Systems, Ames, Iowa, August 18-21 1996.