Programmable-weight building blocks for analog VLSI neural network processors

Analog Integrated Circuits and Signal Processing

Volumn 9, Issue 3, 1996, Pages 215-230

  Chang, Robert C ^a,b   Sheu, Bing J ^a,b,c,d,e   Choi, Joongho ^a,f   Chen, David Cheng Hsiung ^a,c  

^a University of Southern California ^*  (United States)

^b IEEE

^c UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^d NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^e Eta Kappa Nu

^f University of Seoul   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG STORAGE; COMPUTER CONTROL SYSTEMS; GENERAL PURPOSE COMPUTERS; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; NETWORK COMPONENTS; NEURAL NETWORKS; PARALLEL PROCESSING SYSTEMS;

ANALOG PROCESSORS; GENERAL PURPOSE NEURAL CHIP; PARALLEL FUNCTIONAL UNITS; PROGRAMMABLE CAPABILITY; PROGRAMMABLE WEIGHT BUILDING BLOCK;

VLSI CIRCUITS;

EID: 0030125280     PISSN: 09251030     EISSN: None     Source Type: Journal    
DOI: 10.1007/BF00194906     Document Type: Article

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