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IEEE Electron Device Letters

Volumn 19, Issue 8, 1998, Pages 282-284

Back-gated buried oxide MOSFET's in a high-voltage bipolar technology for bonded oxide/SOI interface characterization

(6) Bashir, R a Wang, F a Greig, W a McGregor, J M b Yindeepol, W a De Santis, J a

a Analog Proc Technol Grp Natl S (United States)

b MAXIM INTEGRATED PRODUCTS (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; ELECTRIC CHARGE; ETCHING; GATES (TRANSISTOR); NATURAL FREQUENCIES; SEMICONDUCTOR JUNCTIONS; SILICON ON INSULATOR TECHNOLOGY; SILICON WAFERS; SUBSTRATES; TEMPERATURE MEASUREMENT;

BONDED ETCH BACK SILICON ON INSULATOR (BESOI) WAFERS; BURIED OXIDES (BOX);

MOSFET DEVICES;

EID: 0032141078 PISSN: 07413106 EISSN: None Source Type: Journal
DOI: 10.1109/55.704400 Document Type: Article

Times cited : (3)

References (6)

1
- 0031377546
- Complementary bipolar process in bonded SOI
- S. Feindt, J. Lapham, and J. Steigemald, "Complementary bipolar process in bonded SOI," in Proc. 1997 Int. SOI Conf., pp. 4-6.
- Proc. 1997 Int. SOI Conf. , pp. 4-6
- Feindt, S.¹ Lapham, J.² Steigemald, J.³

2
- 0027839356
- High-performance CMOS fabricated on ultrathin BESOI with sub-10-nm TTV
- S. S. Iyer, M. J. Tejwani, P. M. Pitner, T. O. Sedgwick, and G. G. Shahidi, "High-performance CMOS fabricated on ultrathin BESOI with sub-10-nm TTV," in Proc. 1993 IEEE Int. SOI Conf.
- Proc. 1993 IEEE Int. SOI Conf.
- Iyer, S.S.¹ Tejwani, M.J.² Pitner, P.M.³ Sedgwick, T.O.⁴ Shahidi, G.G.⁵

3
- 0031336938
- Deep dry etching of SOI for silicon micromachined structures
- M. E. McNie, D. O. King, V. Nayar, M. C. Ward, J. S. Burgess, C. Quinn, and S. Blackstone, "Deep dry etching of SOI for silicon micromachined structures," in Proc. 1997 IEEE Int. SOI Conf., pp. 60-61.
- Proc. 1997 IEEE Int. SOI Conf. , pp. 60-61
- McNie, M.E.¹ King, D.O.² Nayar, V.³ Ward, M.C.⁴ Burgess, J.S.⁵ Quinn, C.⁶ Blackstone, S.⁷

4
- 0031364169
- A 170 V polysilicon-emitter complementary bipolar IC technology with full dielectric isolation
- J. M. McGregor, W. Yindeepol, J. De Santis, K. Brown, R. Bashir, and W. McKeown, "A 170 V polysilicon-emitter complementary bipolar IC technology with full dielectric isolation," in Proc. 1997 Bipolar Circuit Technol. Meet., pp. 183-186.
- Proc. 1997 Bipolar Circuit Technol. Meet. , pp. 183-186
- McGregor, J.M.¹ Yindeepol, W.² De Santis, J.³ Brown, K.⁴ Bashir, R.⁵ McKeown, W.⁶

5
- 84907686115
- A 85 V high-performance silicon complementary bipolar technology for high voltage analog applications
- R. Bashir, D. Chen, F. Hebert, J. De Santis, A. Ramde, S. Hobrecht, H. You, P. Maghsoudnia, P. Meng, and R. Razouk, "A 85 V high-performance silicon complementary bipolar technology for high voltage analog applications," in Proc. 1994 Europ. Solid State Device Res. Conf., pp. 217-220.
- Proc. 1994 Europ. Solid State Device Res. Conf. , pp. 217-220
- Bashir, R.¹ Chen, D.² Hebert, F.³ De Santis, J.⁴ Ramde, A.⁵ Hobrecht, S.⁶ You, H.⁷ Maghsoudnia, P.⁸ Meng, P.⁹ Razouk, R.¹⁰

6
- 0004005306
- New York: Wiley
- S. M. Sze, Physics of Semiconductor Devices. New York: Wiley, 1981, p. 447.
- (1981) Physics of Semiconductor Devices , pp. 447
- Sze, S.M.¹

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