High performance CMOS fabricated on ultrathin BESOI with sub-10 NM TTV

IEEE International SOI Conference

Volumn , Issue , 1993, Pages 134-135

  Iyer, S S ^a   Tejwani, M J ^a   Pitner, P M ^a   Sedgwick, T O ^a   Shahidi, G G ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BONDING; CHARACTERIZATION; CMOS INTEGRATED CIRCUITS; ETCHING; GATES (TRANSISTOR); ION IMPLANTATION; MOSFET DEVICES; SEMICONDUCTOR DOPING; SPECTROMETRY; WSI CIRCUITS;

BICMOS TECHNOLOGY; EPITAXIAL PROCESS; ETCH BACK SILICON ON INSULATOR; GATE DELAY; PLASMA BASED THINNING PROCESS; REFLECTANCE SPECTROMETRY; SOI WAFER; TOTAL THICKNESS VARIATION; ULTRA THIN BOND;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0027839356     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)