On-Line Error Detection for Bit-Serial Multipliers in GF(2m)

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 13, Issue 1, 1998, Pages 29-40

  Fenn, Sebastian ^a,b,c   Gossel, Michael ^b,d,e,f   Benaissa, Mohammed ^a,g,h   Taylor, David ^a,i  

^a UNIVERSITY OF HUDDERSFIELD   (United Kingdom)

^b UNIVERSITY OF POTSDAM   (Germany)

^c IEEE   (United Kingdom)

^d FRIEDRICH SCHILLER UNIVERSITY JENA   (Germany)

^e DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

^f Saxonian Academy of Sciences   (Germany)

^g NEWCASTLE UNIVERSITY   (United Kingdom)

^h VLSI   (United Kingdom)

ⁱ IEE Professional Group E3   (United Kingdom)

Author keywords

Finite fields; Multipliers; On line error detection; Parity checking

Indexed keywords

COMPUTER CIRCUITS; COMPUTER SIMULATION; COMPUTER SYSTEM RECOVERY; ERROR DETECTION; LOGIC GATES;

BIT-SERIAL MULTIPLIERS; PARITY CHECKING;

COMPUTER TESTING;

EID: 0032131587     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008333132366     Document Type: Article

References (23)

1. R.L. Rivest, A. Shamir, and L.A. Adleman, "A Method for Obtaining Digital Signatures and Public Key Cryptosystems," Comm. ACM, Vol. 21, pp. 120-126, Feb. 1978.
2. F.J. Mac Williams and N.J.A. Sloane, The Theory of Error-Correcting Codes, North-Holland, New York, 1977.
3. E.R. Berlekamp, "Bit-Serial Reed-Solomon Encoders," IEEE Trans. on Info. Theory, Vol. 28, pp. 869-874, Nov. 1982.
4. J.L. Massey and J.K. Omura, "Computational Method and Apparatus for Finite Field Arithmetic," European. Patent, App. No. 81110018.9, June 1983.
5. m) Using Irreducible All One Polynomials," IEE Proc. Computers and Digital Techniques, Vol. 144, pp. 391-393, Nov. 1997.
6. m) over the Dual Basis," IEEE Trans. Comp., Vol. 45, No. 3, pp. 319-327, March 1996.
7. m)," LNCS-357, Proc. AAECC-6, Rome, Italy, Springer-Verlag, July 1988, pp. 297-309.
8. M. Morii, M. Kasahara, and D.L. Whiting, "Efficient Bit-Serial Multiplication and the Discrete-Time Wiener-Hopft Equation over Finite Fields," IEEE Trans. Info. Theory, Vol. 35, pp. 1177-1183, Nov. 1989.
9. M. Wang and I.F. Blake, "Bit-Serial Multiplication in Finite Fields," SIAM J. Discrete Maths., Vol. 3, pp. 140-148, Feb. 1990.
10. F. Sellers, M. Hsiao, and L. Bearnson, Error Detecting Logic for Digital Computers, McGraw-Hill, New York, 1968.
11. T.R.N. Rao and E. Fujiwara, Error Control Coding for Computer Systems, Prentice Hall, New York, 1989.
12. M. Gössel and S. Graf, Error Detection Circuits, McGraw-Hill, London, New York, 1993.
13. D.K. Pradhan, Fault-Tolerant Computer System Design, Prentice Hall, Upper Saddle River, New Jersey, 1996.
14. S.K. Gupta and D.K. Pradhan, "Can Concurrent Checkers Help BIST?" Proc. Intl. Test Conference, 1992, pp. 140-150.
15. E.S. Sogomonyan, "Concurrent Error-Detection Circuit Evaluation," Report Max-Planck-Society, University of Potsdam, MPI-I-94-605, Sept. 1994.
16. Vl.V. Saposhnikov, A. Dmitriev, M. Gössel, and V.V. Saposhnikov, "Self-Dual Parity Checking - A New Method for On-Line Testing," Proc. 14th IEEE VLSI Test Symposium, Princeton, New Jersey, USA, May 1996, pp. 162-168.
17. M. Gössel and E.S. Sogomonyan, "A Parity-Preserving Multi-Input Signature Analyzer and Its Application for Concurrent Checking and BIST," Journal of Electronic Testing: Theory and Applications, Vol. 8, pp. 165-177, 1996.
18. H. Fujiwara and A. Yamamoto, "Parity-Scan Design to Reduce the Cost of Test Application," Proc. Intl. Test Conference, 1992, pp. 283-292.
19. n)," Discrete Applied Maths., pp. 142-169, 1988/89.
20. R. Lidl and H. Niederreiter, An Introduction to Finite Fields and Their Applications, Cambridge University Press, Cambridge, 1986.
21. m)," Information and Computation, Vol. 83, pp. 21-40, 1989.
22. m)," IEEE Trans. Comp., Vol. 41, pp. 962-971, Aug. 1992.
23. M.A. Hasan, M.Z. Wang, and V.K. Bhargava, "A Modified Massey-Omura Parallel Multiplier for a Class of Finite Fields," IEEE Trans. Comp., Vol. 42, pp. 1278-1280, Oct. 1993.