Bit-serial multiplication in GF(2m) using irreducible all-one polynomials

IEE Proceedings: Computers and Digital Techniques

Volumn 144, Issue 6, 1998, Pages 391-393

  Fenn, S T J ^a   Parker, M G ^b   Benaissa, M ^b   Taylor, D ^b  

^a UNIVERSITY OF HUDDERSFIELD   (United Kingdom)

^b UNIVERSITY OF BRADFORD   (United Kingdom)

Author keywords

Bit serial multipliers; Cryptography; Reeil sotoinoii codes; VLSI

Indexed keywords

CODES (SYMBOLS); CRYPTOGRAPHY; DIGITAL ARITHMETIC; POLYNOMIALS; VLSI CIRCUITS;

BIT SERIAL MULTIPLIERS; REED-SOLOMON CODES;

MULTIPLYING CIRCUITS;

EID: 0031270233     PISSN: 13502387     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cdt:19971586     Document Type: Article

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