Behavioral Level Noise Modeling and Jitter Simulation of Phase-Locked Loops with Faults Using VHDL-AMS

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 13, Issue 1, 1998, Pages 7-17

  Godambe, Nihal J ^a,c,d   Shi, C J Richard ^b,d,e,f,g  

^a MOTOROLA INC   (United States)

^b University of Washington   (United States)

^c INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

^d UNIVERSITY OF IOWA   (United States)

^e FUDAN UNIVERSITY   (China)

^f UNIVERSITY OF WATERLOO   (Canada)

^g Analogy Inc   (United States)

Author keywords

Analog test; Behavioral fault modeling; Fault modeling; Fault simulation; Jitter; Noise

Indexed keywords

COMPUTER SIMULATION; ERROR DETECTION; MATHEMATICAL MODELS; PHASE LOCKED LOOPS; PRINTED CIRCUIT TESTING; SPURIOUS SIGNAL NOISE; VARIABLE FREQUENCY OSCILLATORS;

ANALOG TESTING; BEHAVIORAL LEVEL NOISE MODELING;

COMPUTER TESTING;

EID: 0032131084     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008329031457     Document Type: Article

References (32)

1. L. Milor and A.L. Sangiovanni-Vincentelli, "Minimizing Production Test Time to Detect Faults in Analog Circuits," IEEE Trims. Computer-Aided Design, Vol. 13, No. 6, pp. 796-813, June 1994.
2. W.H. Kao, R. Voorakaranam, and A. Chatterjee, "AHDL-Based Analog Behavioral Fault Modeling and Simulation," Proc. Analog & Mixed-Signal Applications Conf., San Jose, CA, July 1997, pp. 93-96.
3. A. Meixner and W. Maly, "Fault Modeling for the Testing of Mixed Integrated Circuits," Proc. IEEE Int. Test Conf., 1991, pp. 564-572.
4. C.-Y. Pan, K.-T. Cheng, and S. Gupta, "A Comprehensive Fault Macromodel for Opamps," Proc. IEEE Int. Conf. Computer-Aided Design, 1994, pp. 344-349.
5. M. Soma, "An Experimental Approach to Analog Fault Models," Proc. IEEE Custom Integrated Circuits Conf., 1991, pp. 13.6.1-13.6.4.
6. R.J.A. Harvey, A.M.D. Richardson, E.M.J.G. Bruls, and K. Baker, "Analogue Fault Simulation based on Layout Dependent Fault Models," Proc. Int. Test Conf., 1994, pp. 641-648.
7. F.C.M. Kuijstermans, M. Sachdev, and A.P. Thijssen, "Defect-Oriented Test Methodology for Complex Mixed-Signal Circuits," Proc. Int. Test Conf., 1995, pp. 18-23.
8. C. Sebeke, J.P. Teixeira, and M.J. Ohletz, "Automatic Fault Extraction and Simulation of Layout Realistic Faults for Integrated Analogue Circuits," Proc. European Test Conf., 1995, pp. 464-468.
9. G. Devarayanadurg, P. Goteti, and M. Soma, "Hierarchy Based Statistical Fault Simulation for Mixed-Signal ICs," Proc. IEEE Int. Test Conf., Oct. 1996, pp. 521-527.
10. C.-J. Shi and N.J. Godambe, "Behavioral Fault Modeling and Simulation of Phase Locked Loops using a VHDL-AMS Like Language," Proc. IEEE ASIC Conf. and Exhibit, 1996, pp. 245-250.
11. C.-Y. Chao, H.-J. Lin, and L. Milor, "Optimal Testing of VLSI Analog Circuits," IEEE Trans. Computer-Aided Design, Vol. 16, No. 1, pp. 58-77, Jan. 1997.
12. E. Liu, W. Kao, E. Felt, and A. Sangiovanni-Vincentelli, "Analog Testability Analysis and Fault Diagnosis using Behavioral Modeling," Proc. IEEE Custom Integrated Circuits Conf., San Diego, CA, May 1994, pp. 413-416.
13. M. Franz, T.C. Whang, and W. Chou, "A 240 MHz Phase-Locked-Loop Circuit Implemented as a Standard Macro on CMOS SOG Gate Arrays," Proc. IEEE Custom Integrated Circuits Conf., 1992, pp. 25.1.1-25.1.4.
14. B. Razavi, "Analysis, Modeling, and Simulation of Phase Noise in Monolithic Voltage-Controlled Oscillators," Proc. IEEE Custom Integrated Circuits Conf., 1995, pp. 14.5.1-14.5.4.
15. W.E. Thain and J.A. Connelly, "Simulating Phase Noise in Phase-Locked Loops with a Circuit Simulator," Proc. IEEE Int. Symp. Circuits Syst., 1995, Vol. 3, pp. 1760-1763.
16. N.H.E. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective, 2nd edition, Addison-Wesley, 1993.
17. H. Xue, C.N. Di, and J.A.G. Jess, "A Net-Oriented Method for Realistic Fault Analysis," Proc. IEEE Int. Conf. Computer-Aided Design, Nov. 1993, pp. 78-84.
18. N.J. Godambe, "Behavioral Fault Modeling for a Mixed-Signal PLL," Master thesis, Department of Electrical and Computer Engineering, University of Iowa, Dec. 1996.
19. J.C. Ju, V.B. Rao, and R.A. Saleh, "Consistency Checking and Optimization of Macro Models," IEEE Trans. Computer-Aided Design, Vol. 10, No. 8, pp. 957-967, Aug. 1991.
20. C.-J. Shi and M. Tian, "Simulation and Sensitivity of Linear Analog Circuits under Parameter Variations by Robust Interval Analysis," ACM Transactions on Design Automation of Electronic Systems, (to appear) Vol. 4, No. 3, July 1999.
21. M.W Tian and C.-J. Shi, "Rapid Frequency-Domain Analog Fault Simulation under Parameter Tolerances," Proc. 34th IEEE/ACM Design Automation Conf., Anaheim, CA, June 1997, pp. 275-280.
22. C.D. Motchenbacher and J.A. Connelly, Low Noise Electronic System Design, John Wiley, 1993.
23. "Definition of Analog and Mixed-Signal Extensions to IEEE Standard VHDL," IEEE 1076.1 Working Group Document, HDL-A is Mentor Graphics's implementation of an early draft of this standard, April 1998.
24. P. Bolcato and R. Poujois, "A New Approach for Noise Simulation in Transient Analysis," Proc. IEEE Int. Symp. Circuits Syst., May 1992, pp. 887-890.
25. A. Demir, E. Liu, A.L. Sangiovanni-Vincentelli, and I. Vassiliou, "Behavioral Simulation Techniques for Phase/Delay-Locked Systems," Proc. IEEE Custom Integrated Circuits Conf., 1994, pp. 21.3.1-21.3.4.
26. B. Kim, T.C. Weigandt, and P.R. Gray, "PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design," Proc. IEEE Int. Symp. Circuits Syst., June 1994, pp. 31-34.
27. F.M. Gardner, "Charge Pump Phase-Lock Loops," IEEE Trans. Comm., Vol. 28, No. 11, pp. 1849-1858, Nov. 1980.
28. J. McNeill, "Jitter in Ring Oscillators," Proc. IEEE Int. Symp. Circuits Syst., June 1994, pp. 201-204.
29. I.A. Young, J.K. Greason, and K.L. Wong, "A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors," IEEE J. Solid-State Circuits, Vol. 27, pp. 1599-1607, Nov. 1992
30. A.A. Abidi and R.G. Meyer, "Noise in Relaxation Oscillators," IEEE J. Solid-State Circuits, Vol. 18, No. 6, pp. 794-802, Dec. 1983.
31. A. Demir, E. Liu, and A.L. Sangiovanni-Vincentelli, "Time-Domain Non-Monte Carlo Noise Simulation for Non-Linear Dynamic Circuits with Arbitrary Excitations," IEEE Trans. Computer-Aided Design, Vol. 15, No. 15, pp. 493-504, May 1996.
32. I.E. Getreu, "Behavioral Modeling of Analog Blocks Using the SABER Simulator," Proc. Midwest Symp. Circuits Syst., Aug. 1989.