Design and implementation of a 5 × 5 trits multiplier in a quasi-adiabatic ternary CMOS logic

IEEE Journal of Solid-State Circuits

Volumn 33, Issue 7, 1998, Pages 1111-1116

  Mateo, Diego ^a   Rubio, Antonio ^a,b,c,d  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b Indust Eng Faculty of Barcelona   (Spain)

^c Industrial Engineering Faculty (UPC)

^d UNIVERSITAT DE LES ILLES BALEARS   (Spain)

Author keywords

Adiabatic switching; Low power digital design; Low power multiplier; Ternary CMOS logic

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT;

ADIABATIC SWITCHING;

MULTIPLYING CIRCUITS;

EID: 0032123718     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.701275     Document Type: Article

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