Quasi-adiabatic ternary CMOS logic

Electronics Letters

Volumn 32, Issue 2, 1996, Pages 99-101

  Mateo, D ^a   Rubio, A ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

CMOS logic circuits; Ternary logic

Indexed keywords

ADDERS; ALGEBRA; CMOS INTEGRATED CIRCUITS; LOGIC CIRCUITS; LOGIC GATES; MATHEMATICAL MODELS; SEMICONDUCTING SILICON; SWITCHING CIRCUITS;

ADIABATIC BINARY LOGICS; CMOS LOGIC CIRCUITS; POSITIVE TERNARY INVERTER; QUASI ADIABATIC TERNARY; SIMPLE TERNARY MAXIMUM; SIMPLE TERNARY MINIMUM; TERNARY LOGIC; YOLI-ROSENFIELD ALGEBRA;

INTEGRATED CIRCUIT LAYOUT;

EID: 0029772274     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19960082     Document Type: Article

References (6)

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3. YOELI, M., and ROSENFELD, G.: 'Logic design of ternary switching circuits', IEEE Trans., 1965, EC-14, pp. 19-29
4. WANG, J.S., WU, C.Y., and TSAI, M.K.: 'Low power dynamic ternary logic', IEE Proc. G, Electron. Circuits Syst., 1988, 135, (6), pp. 221-230
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6. YOUNIS, S.G., and KNIGHT, T.F.: 'Asymptotically zero energy split-level charge recovery logic'. Proc. Int. Workshop Low Power Design, Napa, 1994, pp. 177-182