A compact neural network for partial-response maximum-likelihood detectors: Algorithmic study

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 45, Issue 7, 1998, Pages 848-856

  Chou, Eric Y ^a,b   Sheu, Bing J ^a,b   Wang, Michelle Yibing ^c  

^a IEEE   (United States)

^b University of Southern California   (United States)

^c HEWLETT PACKARD COMPANY   (United States)

Author keywords

Communication; Distributed parallel processing; Maximum likelihood sequence estimation; Neural networks; Partial response

Indexed keywords

ALGORITHMS; BIT ERROR RATE; COMPUTATIONAL COMPLEXITY; COMPUTER AIDED NETWORK ANALYSIS; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUIT LAYOUT; PARALLEL PROCESSING SYSTEMS; SIGNAL DETECTION; SIGNAL FILTERING AND PREDICTION; SIGNAL INTERFERENCE; VLSI CIRCUITS;

DIGITAL VITERBI ALGORITHMS; PARTIAL RESPONSE MAXIMUM LIKELIHOOD (PRML) SEQUENCE DETECTION;

NEURAL NETWORKS;

EID: 0032121037     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.700932     Document Type: Article

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