Fault-tolerant self-organizing map implemented by wafer-scale integration

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 6, Issue 2, 1998, Pages 257-265

  Yasunaga, Moritoshi ^a,b   Hachiya, Ippei ^b   Moki, Keiji ^c   Kim, Jung Hwan ^a,d  

^a IEEE   (Japan)

^b UNIVERSITY OF TSUKUBA   (Japan)

^c HITACHI LTD   (Japan)

^d UNIVERSITY OF LOUISIANA AT LAFAYETTE   (United States)

Author keywords

Defect; Fault tolerance; Neural network; Self organizing map; Wafer scale integration

Indexed keywords

COMPUTER SIMULATION; FAULT TOLERANT COMPUTER SYSTEMS; ITERATIVE METHODS; WSI CIRCUITS;

SELF ORGANIZING MAPS (SOM);

NEURAL NETWORKS;

EID: 0032095725     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.678883     Document Type: Article

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