Performance evaluation of neural network hardware using time-shared bus and integer representation architecture

IEICE Transactions on Information and Systems

Volumn E79-D, Issue 6, 1996, Pages 888-896

  Yasunaga, Moritoshi ^a   Ochiai, Tatsuo ^a  

^a UNIVERSITY OF TSUKUBA   (Japan)

Author keywords

Neural networks; Parallel computing; Parallel programming language; Performance evaluation; Scalability

Indexed keywords

ALGORITHMS; BACKPROPAGATION; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER PROGRAMMING LANGUAGES; COMPUTER SIMULATION; COMPUTER SYSTEMS PROGRAMMING; DIGITAL ARITHMETIC; EVALUATION; LEARNING SYSTEMS; PARALLEL PROCESSING SYSTEMS; PERFORMANCE;

ENGLISH PRONUNCIATION REASONING TASK; FLOATING POINT REPRESENTATION ARCHITECTURE; INTEGER REPRESENTATION ARCHITECTURE; MIRROR WEIGHT ASSIGNMENT; PARALLEL PROGRAMMING LANGUAGE; TIME SHARED BUS;

NEURAL NETWORKS;

EID: 0030164447     PISSN: 09168532     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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