A complete pipelined parallel CORDIC architecture for motion estimation

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 45, Issue 5, 1998, Pages 653-660

  Chen, Jie ^a   Ray Liu, K J ^a  

^a UNIVERSITY OF MARYLAND   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; IMAGE CODING; IMAGE COMMUNICATION SYSTEMS; MATHEMATICAL TRANSFORMATIONS; PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS; REAL TIME SYSTEMS; STANDARDS;

DISCRETE COSINE TRANSFORMS (DCT); MOTION ESTIMATION; MOTION PICTURE EXPERTS GROUP (MPEG) STANDARDS;

COMPUTER ARCHITECTURE;

EID: 0032075141     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.673651     Document Type: Article

References (7)

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3. Y. H. Hu, "CORDIC-based VLSI architectures for digital signal processing," IEEE Signal Processing Mag., pp. 16-35, July 1992.
4. U.-V. Koc and K. J. R. Liu, "Discrete cosine/sine-transform based motion estimation," in Proc. IEEE Int. Conf. on Image Processing, Austin, TX, vol. 3, Nov. 1994, pp. 771-775; also, IEEE Trans. Image Processing, to be published.
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7. K. K. Parhi, C.-Y. Wang, and A. P. Brown, "Synthesis of control circuits in folded pipelined DSP architectures," IEEEJ. Solid-State Circuits, vol. 27, pp. 29-43, Jan. 1992.