Clock skew reduction in asic logic design: a methodology for clock tree management alessandro balboni, claudio costi, massimo pellencin, andrea quadrini, and donatella sciuto

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 17, Issue 4, 1998, Pages 344-356

  Balboni, A ^a   Pellencin, M ^b   Quadrini, A ^c  

^a Design Methodology and Tools Laboratory   (Italy)

^b UNIVERSITY OF VICTORIA   (Canada)

^c POLITECNICO DI MILANO   (Italy)

Author keywords

Clock skew; Clock tree; Logic synthesis; Placement; Routing

Indexed keywords

ALGORITHMS; HEURISTIC METHODS; LOGIC DESIGN; LOGIC GATES; OPTIMIZATION; SYNCHRONIZATION; TIMING CIRCUITS; TREES (MATHEMATICS);

CLOCK SKEW REDUCTION; LOGIC SYNTHESIS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0032043292     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.703824     Document Type: Article

References (18)

1. S. Boon, S. Butler, R. Byrne, B. Setering, M. Casalanda, and A. Scherf, "High performance clock distribution for CMOS ASICS," in IEEE Custom Integrated Circuits Conf., 1989.
2. T.-H. Chao, Y.-C. Hsu, and J.-M. Ho, "Zero skew clock net routing," in Proc. 29th ACM/IEEE Design Automation Conf., 1992.
3. J. D. Cho and M. Sarrafzadeh, "A buffer distribution algorithm for high-speed clock routing," in Proc. 30th ACM/IEEE Design Automation Conf., 1993.
4. J. P. Cohoon, D. S. Richards, and J. S. Salowe, "A linear-time Steiner tree routing algorithm for terminals on the boundary of a rectangle," in IEEE Int. Conf. Computer-Aided Design, Nov. 1988.
5. J. Cong, A. B. Kahng, and G. Robins, "Matching-based methods for high-performance clock routing," IEEE Trans. Computer-Aided Design, Aug. 1993.
6. W. E. Donath, R. J. Norman, B. K. Agrawal, S. E. Bello, S. Y. Han, J. M. Kurtzberg, P. Lowy, and R. I. McMillan, "Timing driven placement using complete path delays," in Proc. 27th ACM/IEEE Design Automation Conf., 1990.
7. M. Edahiro, "Minimum skew and minimum path length routing, NEC Res. Develop., vol. 32, no. 4, 1991.
8. "A clustering-based optimization algorithm in zero-skew routings," in Proc. 30th ACM/IEEE Design Automation Conf., 1993.
9. E. G. Friedman and S. Powell, "Design and analysis of a hierarchical clock distribution system for synchronous standard cell/macrocell VLSI," IEEEJ. Solid-State Circuits, vol. SC-21, Apr. 1986.
10. M. A. B. Jackson, A. Srinivasan, and E. S. Kuh, "Clock routing for high performance IC's," in Proc. 27th ACM/IEEE Design Automation Conf., 1990.
11. A. Kahng, J. Cong, and G. Robins, "High-performance clock routing based on recursive geometric matching," in Proc. 28th ACM/IEEE Design Automation Conf., 1991.
12. Y.-M. Li and M. A. Jabri, "A zero-skew clock routing scheme for VLSI circuits," in Proc. 1992 Int. Conf. Computer-Aided Design, 1992.
13. C. Nakata, "Delay and timing methods for CMOS ASIC's," Motorola Semiconductor Appl. Note, 1991.
14. "Design compiler," Synopsys Reference Manual, 1993.
15. R.-S. Tsay, "Exact zero skew," in IEEE Int. Conf. Computer-Aided Design, Nov. 1991.
16. S. H. Unger and C.-J. Tan, "Clocking schemes for high-speed digital systems," IEEE Trans. Comput., vol. C-35, Oct. 1986.
17. N. Sherwani, W. Khan, and M. Hossain, "Zero skew clock routing in multiple-clock synchronous systems," in Proc. 1992 Int. Conf. Computer-Aided Design, 1992.
18. D. F. Wann and M. A. Franklin, "Asynchronous and clocked control structures for VLSI based interconnection network," IEEE Trans. Comput., vol. C-32, Mar. 1983.