Single-electron logic systems based on the binary decision diagram

IEICE Transactions on Electronics

Volumn E81-C, Issue 1, 1998, Pages 49-56

  Asahi, Noboru ^a  

^a HOKKAIDO UNIVERSITY   (Japan)

Author keywords

Adder; BDD; Binary decision diagram; Comparator; Logic circuit; Single electron

Indexed keywords

ADDERS; BINARY SEQUENCES; COMPARATOR CIRCUITS; COMPUTER SIMULATION; ELECTRON TRANSPORT PROPERTIES; LOGIC CIRCUITS; PIPELINE PROCESSING SYSTEMS; THERMAL NOISE;

BINARY DECISION DIAGRAMS (BDD);

DECISION TABLES;

EID: 0031702415     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (5)

1. N. Asahi, M. Akazawa, and Y. Amemiya, "Binarydecision-diagram device," IEEE Trans. Electron Devices, vol.42, no.ll, pp. 1999-2003, 1995.
2. N. Asahi, M. Akazawa, and Y. Amemiya, "Single-electron logic device based on the binary decision diagram," IEEE Trans. Electron Devices, vol.44, no.7, pp.1109-1116, 1997.
3. S.D. Akers, "Binary decision diagrams," IEEE Trans. Cornput., vol.C-27, no.6, pp.509-516, 1978.
4. R.E. Bryant, "Graph-based algorithms for Boolean function manipulation," IEEE Trans. Comput., vol.C-35, no.8, pp.677-691, 1986.
5. N. Kuwamura, K. Taniguchi, and C. Hamaguchi, "Simulation of single-electron logic circuits," IEICE Trans., V01.J77-C-II, no.5, pp.221-228, May 1994.