Multiprocessor validation of the pentium pro

Computer

Volumn 29, Issue 11, 1996, Pages 47-53

  Marr, Deborah T ^a,b,c,d   Natarajan, Subramanian ^a,e,f   Thakkar, Shreekant ^a,d,g,h   Zucker, Richard ^a,i,j,k  

^a INTEL CORPORATION   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c Department of Molecular Biology and Genetics

^d IEEE

^e UNIVERSITY OF MADRAS   (India)

^f UNIVERSITY OF FLORIDA   (United States)

^g UNIVERSITY COLLEGE LONDON   (United Kingdom)

^h UNIVERSITY OF MANCHESTER   (United Kingdom)

ⁱ UNION COLLEGE   (United States)

^j UNIVERSITY OF WASHINGTON   (United States)

^k ACM

more..

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTING; COMPUTER SYSTEMS; DATABASE SYSTEMS; MICROCOMPUTERS; PRODUCTION; SEMICONDUCTING SILICON; STANDARDS;

FUNCTIONALITY; MICROBENCHMARKS; MULTIPROCESSOR VALIDATION; PRODUCTION SYSTEM; RANDOM TEST GENERATION;

MULTIPROCESSING SYSTEMS;

EID: 0030284924     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/2.544237     Document Type: Review

References (9)

1. R. Colwell and R. Steck, "A 0.6 Micron BiCMOS Processor with Dynamic Execution," Proc. IEEE Solid State Circuits Conf., IEEE Press, Piscataway, N.J., 1995.
2. K. Gharachorloo et al., "Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors," Proc. 17th Int'l Symp. Computer Architecture, IEEE Computer Soc. Press, Los Alamitos, Calif., 1990, pp. 15-26.
3. J. Archibald and J.L. Baer, "Cache Coherence Protocols: Evaluation Using a Multiprocessor Simulation," ACM Trans. Computer Systems, Nov. 1986, pp. 273-298.
4. M. Bell and T. Holman, "Pentium Pro Workstation/Server PCI Chipset," Proc. 41st IEEE Int'l Computer Conf., IEEE Computer Soc. Press, Los Alamitos, Calif., 1996, pp. 388-394.
5. N. Sarangdhar and G. Singh, "An Overview of Pentium Pro Processor Bus," Proc. 41st IEEE Int'l Computer Conf., IEEE Computer Soc. Press, Los Alamitos, Calif., 1996, pp. 383-387.
6. G. Cai, "Architectural and Multiprocessor Design Verification of the PowerPC 604 Data Cache," Proc. 14th Int'l IEEE Phoenix Conf. Computers and Communications, IEEE Computer Soc. Press, Los Alamitos, Calif., 1995, pp. 383-388.
7. C. Montemayor et al., "Multiprocessor Design Verification for the PowerPC 620 Microprocessor," Proc. 1995 Int'l Conf. Computer Design, IEEE Computer Soc. Press, Los Alamitos, Calif., 1995, pp. 188-195.
8. K. Gharachorloo, A. Gupta, and J. Hennessy, "Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors," Tech. Report CSL-TR-93-568, Stanford Univ., Palo Alto, Calif., 1993.
9. S. Woo et al., "The Splash-2 Programs: Characterization and Methodological Considerations," Proc. 22nd Int'l Symp. Computer Architecture, IEEE Computer Soc. Press, Los Alamitos, Calif., 1995, pp. 24-36.