Matrix unit cell scheduler (MUCS) for input-buffered ATM switches

IEEE Communications Letters

Volumn 2, Issue 1, 1998, Pages 20-23

  Duan, Haoran ^a,b   Lockwood, John W ^a   Kang, Sung Mo ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b HEWLETT PACKARD COMPANY   (United States)

Author keywords

ATM cell scheduler; ATM switches; Input queuing (IQ) architecture; MUCS

Indexed keywords

ALGORITHMS; BANDWIDTH; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; HEURISTIC METHODS; SWITCHING NETWORKS; TELECOMMUNICATION LINKS;

MATRIX UNIT CELL SCHEDULER (MUCS); SOFTWARE PACKAGE HSPICE;

ASYNCHRONOUS TRANSFER MODE;

EID: 0031647315     PISSN: 10897798     EISSN: None     Source Type: Journal    
DOI: 10.1109/4234.658616     Document Type: Article

References (11)

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