Process modeling for sequential build-up of multi-layered structures

Proceedings - Electronic Components and Technology Conference

Volumn Part F133492, Issue , 1998, Pages 353-361

  Dunne, R C ^a   Sitaraman, S K ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

NETWORK COMPONENTS; PROCESS ENGINEERING; DEFORMATION; MATHEMATICAL MODELS; RESIDUAL STRESSES; STRESS ANALYSIS; SUBSTRATES;

DEFORMATION MODELS; HIGH DENSITY INTERCONNECTS; INTERMEDIATE STAGE; MULTI-LAYERED STRUCTURE; MULTILAYERED SUBSTRATES; PARAMETRIC PROCESS; POLYMER DEPOSITION; PROCESSING TECHNIQUE;

SUBSTRATES; ELECTRONICS PACKAGING;

AXIAL STRESS; HIGH DENSITY INTERCONNECTS (HDI); WARPAGE;

EID: 0031630758     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.1998.678718     Document Type: Conference Paper

References (9)

1. Cifuentes, A. O., I. A. Shareef, 1992, "Modeling of Multilevel Structures: A General Method of Analyzing Stress Evolution during Processing, " IEEE Transactions on Semiconductor Manufacturing, Vol. 5, No. 2, pp. 128-137.
2. Cifuentes, A. O., I. A. Shareef, 1993, "Some Modeling Issues on the Finite Element Computation of Thermal Stresses in Metal Lines, " Journal of Electronic Packaging, Transactions of the ASME, vol. 115, pp. 392-403.
3. Dunne, R., Smith, K., S. Sitaraman, 1997a, "Thermo-mechanical behavior of High-density Interconnect Vias, " Advances in Electronic Packaging, Vol. 2, Proceedings of INTERPACK June 97, pp. 1305-1311.
4. Dunne R., S. Sitaraman, 1997b, "Warpage and Interfacial Stress Distribution in a Single-Level-Integrated-Module (SLIM), " Journal of Electronic Packaging, Transactions of the ASME, vol. 119, pp. 197-203.
5. Morgan, H. S., 1995, "Thermal Stresses in Layered Electrical Assemblies Bonded with Solder, " Journal of Electronic Packaging, Transactions of the ASME, Vol. 113, pp. 350-354.
6. Sundararaman, V., Sitaraman, S. K., "Interfacial Fracture Toughness Determination for Reliable Design of Multi-Layered Structures, " 97-WA/EEP-l, 9th Symposium on Mechanics of Surface Mount Assembly, ASME International Mechanical Congress and Exposition, Dallas, TX, Nov. 1997.
7. Wu, S. X., Yeh, C-P, Hu, K. X., K. Wyatt, 1995, "Process Modeling for MultiChip Module Thin Films Interconnects, " ASME Journal of Cooling and Thermal Design of Electronic Systems, HTD-Vol. 319/EEP-Vol. 15.
8. Wu, S. X., Zhang, C, Yeh, C-P, Wille, S., K. Wyatt, 1997, " Cure Properties and Mechanical Properties of Conductive Adhesives, " pp. 550-553, Proceedings of the 47th Electronic Components and Technology Conference, San Jose, CA.
9. Yin, W-L, 1995, "Interfacial Thermal Stresses in Layered Structures: The Stepped Edge Problem, " Journal of Electronic Packaging, Transactions of the ASME, Vol. 117, pp. 153-157.